Developing fast clock source with deterministic jitter Final review – Part A Yulia Okunev Supervisor -Yossi Hipsh HS-DSL Laboratory, Dept. of Electrical Engineering Technion – Israel Institute of Technology

2 Background In this project I designed fast clock source with deterministic jitter for high speed phenomena experiment. Jitter [1] is the deviation of a periodic signal, in this case, clock source, from its ideal period. Or in other words the period frequency displacement of the signal from its ideal location. System overview: Pulse generator is used to produce electrical input signal. This clock signal will be divided to 8 channels. Each signal passes through delays array and combined in the output. Using Scope we can measure the system output.

Project Top Block diagram 3 Pulse Generator 4nSec Clock Signal divider delays array Clock Signal combiner Output to Scope Two-way coupling

Solution algorithm 4 Passive delays array: We created 8 different length transmission lines which causes the signal to delay respectively to the line length. The lines will be printed on the top/bottom layer of the PCB (microstrip) Passive clock divider/combiner: We created divider (combiner) for the clock signal using resistor divider (combiner)

Theory and calculations

6 Transmission lines Parameters 8 high speed lines, impedance of 50Ω, on top/bottom layer – microstrip lines. Main signal period is 4 nsec. we will create 0.5 nsec clock from the main signal To create between each pair of adjacent transmission lines the required is: 8cm We chose to be smaller than the input signal period. This way the input signal contains the divided signal in one period as shown:

7 Transmission lines Parameters-cont.. We can control by choosing different We can reduce/ increase the propagation time in each line by reducing/ increasing it’s length We will observe the Jitter phenomena as a function on the accuracy of line length Input signal Ideal output Jitter in output

Schematic

9 Schematic-Step 1 At the first step we implemented the divider and the combiner in the same symmetrical way. A basic model of a passive power splitter\combiner: this way there is 50 ohm matching after the signal is divided

10 Schematic-Step 1 Passive delays array Passive clock dividerPassive clock combiner Junction model Passive clock divider Passive clock combiner Is a mirror image of Junction model

11 Schematic-Step 1 We planed to use 16.6ohm from VISHAY that seemed to be available in a wide resistance range. After connecting with VISHAY (and few other companies) we learned that only 50ohm resistors are available in stock. To create 16.6ohm resistor we need to use three 50ohm resistors in parallel –> increases cost X3

12 Schematic-Step 2 We implemented semi –symmetrical junction (to spare resistors and space on the board). It is possible only for the power divider since the signals spreads in all channels simultaneously without reflections back to the source. this way there is 50 ohm matching after the signal is divided

13 Schematic-Step 2 Passive delays array Passive clock dividerPassive clock combiner Junction model Passive clock divider Passive clock combiner Junction model

14 Schematic-Step 3 In order to get an accurate results from the simulation, at this point, we had to design the implementation of the junctions on layout, and than run the simulation with the accurate transmission lines sizes.

Simulation

16 Simulation Input signal to output signal Input signal data: Period =4 nsec Amplitude= mV Output signal data: Amplitude=27.557mV Attenuation between Input signal and Output signal: 30.1dB This is sufficient for our needs

17 Simulation Input signal to output signal We can observe a Transitional Phenomenon that occurs due to signals reflections back to the input. After few clock cycles the output signal stabilizes on a steady DC average voltage. We will look at the signal at its steady state as shown in the next slide.

18 Simulation Output signal to undesired output signal Zoom in on the output We can define a threshold of 24mV that will separate between the positive and negative clock edge. This way we can clearly identify the pulse of our generated clock signal.

19 Simulation output signal The length of the lines, to create between each pair of adjacent transmission lines should be: 0.083m, 0.166m, 0.249m, 0.332m,0.415m 0.498m, 0.581m, 0.664m Main signal period is 4 nsec Generated clock period 0.5 nsec

Board stuck-up and Components

21 Stuck-up We decided to use 4 layer stuck-up, even though 3 layers is enough for our needs it doesn’t make a significant difference in terms of price. And the 4 layers stuck-up is more commonly used in the industry.

22 Components Resistors: Value: 50 ohm. Size: 0603 Power consumption: 0.125W (maximal power in circuit: ) Connectors: BNC

Summary and Steps in PART B

24 Summary We examined the theory and obstacles of real implementation of fast clock source on PCB We took in consideration the stuck-up we will use, the junction implementation, the number of components and their physical size on the PCB We created an accurate and compatible to real implementation simulation We got satisfying results

25 Next steps –PART B Create an accurate drawing of the transmissions line on the board Make a preliminary assessment of the board size Give the files to Ella (CAD designer) for implementation on the PCB using CADENCE (CAD tool) Building an engineering model to demonstrate sustainability

26 Thank you Yulia Okunev

27 Reference [1] [2] Resistors from FRANELL company