FPGA-Based System Design Copyright  2004 Prentice Hall PTR Logic Design Process n Functional/ Non-functional requirements n Mapping into an FPGA n Hardware description languages n Physical design n Example: parity

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Functional requirements n Functionality. –Inputs/output –logic networks Combinational logic Primary inputs Primary outputs

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Non-functional requirements n Performance: –Clock speed is generally a primary requirement. n Size: –Determines manufacturing cost. n Power/energy: –Energy related to battery life, power related to heat. –Many digital systems are power- or energy-limited.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Mapping into an FPGA n Must choose the FPGA: –Capacity. –Pinout/package type. –Maximum speed.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Hardware description languages n Structural description: –A connection of components. n Functional description: –A set of Boolean formulas, state transitions, etc. n Simulation description: –A program designed for simulation. n Major languages: –Verilog. –VHDL. A NAND x

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Logic optimization n Must transform Boolean expressions into a form that can be implemented. –Use available primitives (gates). –Meet delay, size, energy/power requirements. n Logic gates implement expressions. –Must rewrite logic to use the expressions provided by the logic gates. n Maintain functionality while meeting non- functional requirements.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Macros n Larger modules designed to fit into a particular FPGA. –Hard macro includes placement. –Soft macro does not include placement.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Physical design n Placement: –Place logic components into FPGA fabric. n Routing: –Choose connection paths through the fabric. n Configuration generation: –Generate bits required to configure FPGA.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Example: parity n Simple parity function: –P = a0 XOR a1 XOR a2 XOR a3. n Implement with Xilinx ISE.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Xilinx ISE main screen Sources in project Processes for source Source window Output

FPGA-Based System Design Copyright  2004 Prentice Hall PTR New project

FPGA-Based System Design Copyright  2004 Prentice Hall PTR New project info

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Create HDL file

FPGA-Based System Design Copyright  2004 Prentice Hall PTR I/O description

FPGA-Based System Design Copyright  2004 Prentice Hall PTR I/O info

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Empty Verilog description module parity(a,p); input [31:0] a; output p; endmodule

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Verilog with functional code module parity(a,p); input [31:0] a; output p; assign p = ^a; endmodule

FPGA-Based System Design Copyright  2004 Prentice Hall PTR RTL schematic: top-level

FPGA-Based System Design Copyright  2004 Prentice Hall PTR RTL model: implementation

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Example: simulation n Apply stimulus/test vectors. n Look at response/output vectors. n Can’t exhaustively simulate but we can exercise the module. n Simulation before synthesis is faster and easier than simulating the mapped design. –Sometimes want to simulate the mapped design.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Testbench testbench Unit Under Test (UUT) Stimulus Response

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Automatically-created testbench module parity_testbench_v_tf(); // DATE: 11:48:13 11/07/2003 // MODULE: parity // DESIGN: parity // FILENAME: testbench.v // PROJECT: parity // VERSION: // Inputs reg [31:0] a; // Outputs wire p; // Bidirs // Instantiate the UUT parity uut (.a(a),.p(p) ); // Initialize Inputs ‘ifdef auto_init initial begin a = 0; end ‘endif endmodule

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Test vector application code initial begin $monitor("a = %b, parity=%b\n",a,p); #10 a = 0; #10 a = 1; #10 a = 2’b10; #10 a = 2’b11; #10 a = 3’b100; #10 a = 3’b101; #10 a = 3’b110; #10 a = 3’b111; … #10 a = 1024; #10 a = 1025; #10 a = 16’b ; #10 a = 17’b ; #10 a = 17’b ; #10 a = 32’b ; #10 a = 32’b ; #10 a = 32’b ; $finish; end

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Project summary