Glue Card Test Procedures Flavio Fontanelli, Pino Mini`, Mario Sannino.

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Presentation transcript:

Glue Card Test Procedures Flavio Fontanelli, Pino Mini`, Mario Sannino

Glue Card Test Board

Glue Test Board

Glue Card Test Procedures Test Board Procedures 4 X I2C Busses : Each line individually tested enabling on test board it with different GPIO’s from LHCb Connector. For each line: I2C RAM written and then independently read. Dot Matrix display written. Sensor (e.g. Temperature) read. PLX 9030 bus : 256 Kb 32 bit memory written and then independently read. Corresponding bits of LAD and LA lines compared by means of FPGA Xilinx Spartan XL. A 32 bit register written and read on the FPGA 3 X JTAG Busses : tested at the level of the controller. For what the Hub is concerned, by means of proper software, Test Board FPGA can be loaded separately with each different JTAG bus enabled with different GPIO’s from LHCb Connector.