 Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:  Ripple Counters Clock is connected to the flip-flop clock input on the LSB (Least Significant Bit) bit flip-flop For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous Output change is delayed more for each bit toward the MSB (Most Significant Bit). Resurgent because of low power consumption  Synchronous Counters Clock is directly connected to the flip-flop clock inputs Logic is used to implement the desired state sequencing Counters

 How does it work? Since each Q is half the frequency of its clock and provides the clock for the next, the combined output Q0,Q1,Q2 provides a binary count of the clock pulses at CLK, where Q0 is the lsb of the count. Ripple Counter - JK COUNTERS

 These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flop’s state.  The changes “ripple” upward through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. Ripple Counter (continued)

MOD Counter  A 3-bit counter counts 000 to 111 which is 8 states, equivalent to decimal 0 to 7.  On the ninth pulse the counter rolls over from 111 to 000 and starts again.  This is called a 'modulus 8 counter' or 'MOD-8 Counter'

Examples of MOD Counter 1.What is the MOD number of a ripple counter with 5 JKFFS? 2 5 = What is the maximum decimal number count of a MOD-16 counter?4 JKFF 2 4 = 16 = = 15

Example  Design a MOD counter 1. Find smallest n, where2 n > Therefore n = 4 2. Use 4 JKFFs 3. Create an asynchronous CLR when the decimal count output: that is when Q3, Q2, Q1, Q0 : A MOD-10 counter is a MOD-16 counter which clears the output when a count of ten ( 1010) occurs 5. Use this NAND gate to clear the counter

Example (cont)

D-Type Flip-Flops  The most commonly used FF is the delay flip flop or D type flip- flop. It merely imitates the action of a JK flip flop with the K input always being the inversion of the J input When the JK is connected with an inverter between its inputs, there is only one input which always either SETs or RESETs the FF. This is exactly how a D – type FF works. The input D is transferred to the output Q after a clock pulse falling edge. In other words the circuit response to the input is Delayed until the clock pulse arrives.

Registers  Register – a collection of binary storage elements  In theory, a register is sequential logic which can be defined by a state table  More often think of a register as storing a vector of binary values  Frequently used to perform simple data storage and data movement and processing operations

Registers (cont)  If many DFFs are used together, we can store multi-bit numbers. A circuit which stores binary numbers is called a Register. Here we show an 4-bit D – type register.  Before the CLK pulse, the output is holding a previously stored 1001  After the CLK pulse, the output changes and stores the new 1110 number.  The master clear C LR can be used to RESET the stored value to 0000

MULTIPLEXER (MUX)  An electronic "many - to- one" switch  Many inputs - One output  A multiplexer is a device that has a number of data inputs “m”, and number of control inputs “n” and one output, such that m=2n. The output has always the same value as the data input specified by the binary number at the control inputs.

Implementing Truth Tables Using a Multiplexer Instead of AND/OR gate Logic  The select input, connects the logic level on ONE of the input data pins to be transferred to the output Q. If SELECT is 111 then the D7 input is transferred to Q. For instance, if the D2 input = 1, then when S2, S1, S0 = 010, the output will be Q=1. This can used to implement a truth table directly.

Example 1  Design a circuit to give an output Q defined by the function (Q = Σ1,3,5,6)

DECODERS, MULTIPLEXERS (MUX) and DEMULTIPLEXERS DEMUX) DECODERS ( one-of-many)  A decoder is a combinational digital circuit with a number of inputs ‘n’ and a number of outputs ‘m’, where m= 2n.  A decoder has MANY outputs, but it has the property that ONLY ONE of its outputs can be a logic 1 at any one time. The output which becomes 1 is selected by an 'Address Select' input. If the address select input is a 3-bit number, the number of outputs which can be 'address selected' to be logic 1 is 8 [ 2 3 = 8].

EXAMPLE 1

EXAMPLE 2

A 1 to 2 (or a 1 of 2) Decoder

DEMULTIPLEXERS (DEMUX)  A 1 to 8 Demultiplexer. Control of the switch position is electronic.  Sometimes called a 'data distributor  Usually found connected to the output of a multiplexer  Works like a reverse multiplexer  Input is routed to one of the outputs depending on the select input.  A typical demux chip is a 74LS138 ( see lab)

DEMULTIPLEXERS (DEMUX) (cont)