CH71 Chapter 7 Hardware Description Language (HDL) By Taweesak Reungpeerakul

CH72 Contents Introduction Hierarchical Modeling Concepts Basic Concepts Modules and Ports Gate-Level Modeling Dataflow Modeling Behavioral Modeling

CH Introduction HDL: a standard language described digital circuits Model the concurrency of processes found in hardware elements Two popular types: VHDL and Verilog HDL No need to manually place gates to build digital circuits Circuits designed in HDL in order to describe function and data flow

CH74 Typical Design Flow Production-ready Masks Design Specification 1 Behavioral Description 2 RTL Description (HDL) 3 Simulation 4 Design Integration 5 Logic synthesis 6 Gate-level Netlist 7 Logical Verification 8 Auto Place & Route 9 Physical Layout 10 Layout Verification 11 Implementation 12

CH75 Importance of HDLs Designs described at abstract level Cut down design cycle time Analogous to computer programming (easy to develop and debug circuits)

CH76 Popularity of Verilog HDLs Easy to learn and to use Hardware model defined in terms of switches, gates, RTL, or behavior code Several tools support Verilog Libraries provided for postlogic synthesis simulation Allow the users to write custom C

CH Hierarchical Modeling Concepts Design Methodology 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example

CH78 Design Methodology Two types: top-down and bottom-up Top-down:  Top-level Sub-blocks Leaf Cells … Leaf Cells (that cannot further be divided) Bottom-up: build from available blocks and use them for higher-level blocks until top-level

CH79 Top-down Design Methodology Top-down Bottom-up

CH710 4-bit Ripple Carry Counter Counter made up from 4 negedge T_FF T_FF made up from negedge D_FF and inverters

CH711 Design Heirachy

CH712 Modules module ( ); … … endmodule module T_FF (q, clock, reset); … … endmodule Typical module T_flipflop

CH713 Module Instantiation module ripple_carry_counter (q, clk, reset); output [3:0] q; input clk, reset; T_FF tff0 (q[0], clk, reset); T_FF tff1 (q[1], q[0], reset); T_FF tff2 (q[2], q[1], reset); T_FF tff3 (q[3], q[2], reset); endmodule module T_FF (q, clk, reset); output q; input clk, reset; wire d; D_FF dff0 (q, clk, reset); not n1 (d,q); endmodule

CH714 Module Instantiation (2) module D_FF (q, d, clk, reset); output q; input d, clk, reset; reg q; reset or negedge clk) if (reset) q = 1’b0; else q = d; endmodule

CH715 Components of a Simulation

CH716 Stimulus Block and Output Waveforms module stimulus; reg clk, reset; wire [3:0] q; Ripple_carry_counter r1 (q, clk, reset); initial clk = 1’b0; qlways #5 clk = ~clk; initial begin reset = 1’b1; #15 reset = 1’b0; #180 reset = 1’b1; #10 reset = 1’b0; #20 $finish; end initial $monitor($time, “Output q = %d”, q); endmodule

CH717 Output of the Simulation

CH Basic Concepts Lexical Conventions Data Types System Tasks and Compiler Directives

CH719 Lexical Conventions Whitespace \b, \t, \n Comments // ข้อความ 1 บรรทัด /* ข้อความมากกว่า 1 บรรทัด */ Operators a = ~ b; // unary a = b && c; // binary a = b ? c : d; // ternary Number ’ Legal format: ’d, ’h, ’b, ’o Ex. 4’b1011, 8’h9c x is unknown; 6’hx z is high impedance -7’d3: 8-bit of 2’s of 3 String “Hello Verilog” // string Appendix C List of Keywords, System Tasks

CH720 Data Types Value Level 0, 1, x, z Net wire: most declaration Register reg Vectors [high#:low#] หรือ [low#,high#] เช่น reg [7:0] busA; Integer, Real, Time integer, real, time Arrays For reg, integer, time, and vector register Parameters parameter port_id = 5; // constant String Stored in reg เช่น Reg [8*18:1] string_value;

CH721 System Tasks and Compiler Directives System Tasks $ $display usage: $display(p1,p2,…,pn); $monitor usage: $monitor(p1,p2,…,pn); usage: $monitoron; usage: $monitoroff; $stop usage: $stop; $finish usage: $finish; Compiler Directives ‘ ‘define ‘define SIZE 32 ‘include ‘include header.v

CH Modules and Ports Modules Ports  List of Ports  Port Declaration  Port Connection Rules  Connecting Ports to External Signals Hierarchical Names

CH723 Modules

CH724 Components of a Module module SR_latch(Q, Qbar, Sbar, Rbar); output Q, Qbar; input Sbar, Rbar; nand n1(Q, Sbar, Qbar); nand n2(Qbar, Rbar, Q); endmodule module top; wire q, qbar; reg set, reset; SR_latch m1(q, qbar, ~set, ~reset); initial begin $monitor($time, “set = %b, reset=%b, q=%b\n”, set,reset,q); set = 0; reset = 0; #5 reset =1; #5 reset =0; #5 set =1; end endmodule

CH725 Ports List of Ports Port Declaration  input  output  inout//bidirection module fulladd4(sum, c_out, a, b, c_in); output [3:0] sum; output c_cout; input [3:0] a, b; input c_in; … … endmodule Note: If output ports hold their value, they must be declared as reg.

CH726 Ports (2) Port Connection Rules Connecting Ports to External Signals Two ways:  Order list  Name module fulladd4(sum, c_out, a, b, c_in); output [3:0] sum; output c_cout; input [3:0] a, b; input c_in; … endmodule fulladd4 byorder(SUM, C_OUT,A, B, C_IN); fulladd4 byorder(.a(A),.b(B),.c_in(C_IN),.sum(SUM),.c_out(C_OUT));

CH Gate-level Modeling Gate Types  And/Or Gates  Buf/Not Gates  Example Gate Delays  Rise, Fall, and Turn-off Delays  Min/Typ/Max Values  Example

CH728 Gate Types and or xor nand nor xnor Example: Buf/Not Gates  buf  Not  bufif/notif and a1 (out, i1, i2); buf b1 (out, in); not n1 (out, in); notif n2 (out, in, ctrl);

CH729 Example module f_add (sum, c_out, a,b,c_in); output sum, c_out; input a, b, c_in; wire s1,s2,c1; xor n1 (s1, a, b); and n2 (c1, a, b); xor n3 (sum, s1, c_in); and n4 (s2, s1, c_in); or n5 (c_out, s2, c1); endmodule

CH730 Gate Delays Rise, Fall, and Turn-off and #(5) a1(out,i1,i2); //delay of 5 for all transitions and #(4,6) a2(out,i1,i2); //rise = 4, fall =6 bufif0 #(3,4,5) b1(out,i1,ctrl); //rise = 3, fall =4, turn-off =5 Min/Typ/Max Values and #(4:5:6) a1(out,i1,i2); // min=4, typ=5, max=6 and #(3:4:5, 5:6:7) a2(out,i1,i2); // min: rise=3, fall=5, t-off=min(3,5) // typ: rise=4, fall=6, t-off=min(4,6) // max: rise=5, fall=7, t-off=min(5,7) and #(2:3:4, 3:4:5, 4:5:6) a3(out,i1,i2); // min: rise=2, fall=3, t-off=4 // typ: rise=3, fall=4, t-off=5 // max: rise=4, fall=5, t-off=6

CH731 Example module D (out, a, b, c); output out; input a, b, c; wire e; and #(5) a1 (e, a, b); or #(4) o1 (out, e, c); endmodule

CH Dataflow Modeling Continuous Assignments Delays Expressions, Operators, and Operands Operator Types Examples

CH733 Dataflow Modeling (2) Continuous Assignments assign out = i1 & i2; assign addr[7:0] = addr1[7:0]^ addr2[7:0]; assign {c_out, sum[3:0]} = a[3:0] + b[3:0] +c_in; Delays assign #10 out = i1 & i2; Expressions เช่น a ^ b, i1 + i2 Operands เช่น count = count + 1; out1 = r1 ^ r2; Operators เช่น d1 && d2;

CH734 Operator Types Arithmetic * / + - % Logical ! && || Relational > = <= Equality == != === !== Bitwise ~ & | ^ ^~ Reduction & ~& | ~& ^ ^~ Shift >> << Concatenation { } Replication { { } } Conditional ? :

CH735 Examples Multiplexer Full Adder Ripple Counter

CH Behavioral Modeling Structured Procedures Procedural Assignments Timing Controls Conditional Statements Multiway Branching Loops Sequential and Parallel Blocks

CH737 Structured Procedures initial Statement module stimulus; reg a, b; initial begin #5 a = 1’b1; #15 b = 1’b0; end endmodule always Statement module clock_gen; reg clk; initial clk = 1’b0; always #5 clk = ~clk; initial #1000 $finish; endmodule

CH738 Procedural Assignments Blocking Assignment reg x, y, z; reg [7:0] reg_a, reg_b; integer count; initial begin x=0; y=1; z=1; count =0; reg_a = 8’b0; reg_b = reg_a; #5 reg_a[2] = 1’b1; #10 reg_b[6:4] = {x,y,z} count = count+1; end Nonblocking Assignment reg x, y, z; reg [7:0] reg_a, reg_b; integer count; initial begin x=0; y=1; z=1; count =0; reg_a = 8’b0; reg_b = reg_a; #5 reg_a[2] <= 1’b1; #10 reg_b[6:4] <= {x,y,z} count <= count+1; end

CH739 Timing Controls Regular Delay #5 a = 1’b1; Intra-assign Delay a = #5 b + c; a = clk) a = c; q clk) c; Level-sensitive always wait (en) #5 c = c+1;

CH740 Conditional Statements if… else… if ( ) true_statement; else false_statement; if ( ) true_statement_1; else if ( ) true_statement2; else default_statement; Examples if (!a) b = c; if (a<0) b = c; else b = d; if (a>0) a = b; else if (a<0) a = b+c; else $display(“a=0”);

CH741 Multiway Branching case ( ) alt1: statement1; alt2: statement2; …. default: defult_statement; endcase case (ctrl) 2’d0 : y = x+z; 2’d1 : y = x-z; 2’d2 : y = x*z; default : $display(“error”); endcase

CH742 Loops while Loop integer c; initial begin c = 0; while (c<128) begin $display (“count =%d”, c); c = c +1; end for Loop integer c; initial for ( c=0; c<128; c= c+1) $display (“count =%d”, c);

CH743 Sequential and Parallel Blocks Sequential Blocks reg a,c; reg [1:0] x, y; initial begin a = 1’b0; #5 c = 1’b1; #10 x = {a, c}; #20 y = {c, a}; end Parallel Blocks reg a,c; reg [1:0] x, y; initial fork a = 1’b0; #5 c = 1’b1; #10 x = {a, c}; #20 y = {c, a}; join

CH744 Reference S. Palnitkar, Verilog HDL: a Guid to Digital and Synthesis, SunSoft Press, 1996.