Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Topics n Shifters. n Adders and ALUs.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Combinational shifters n Useful for arithmetic operations, bit field extraction, etc. n Latch-based shift register can shift only one bit per clock cycle. n A multiple-shift shifter requires additional connectivity.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Barrel shifter n Can perform n-bit shifts in a single cycle. n Efficient layout. n Does require transmission gates and long wires.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Barrel shifter structure Accepts 2n data inputs and n control signals, producing n data outputs. data 1 data 2 n bits output n bits

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Barrel shifter operation n Selects arbitrary contiguous n bits out of 2n input buts. n Examples: –right shift: data into top, 0 into bottom; –left shift: 0 into top, data into bottom; –rotate: data into top and bottom.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Barrel shifter layout Two-dimensional array of 2n vertical X  n horizontal cells. n Input data travels diagonally upward. Output wires travel horizontally. n Control signals run vertically. Exactly one control signal is set to 1, turning on all transmission gates in that column.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Barrel shifter cell

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Barrel shifter in action

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Analysis n Large number of cells, but each one is small. n Delay is large, considering long wires and transmission gates.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Adders n Adder delay is dominated by carry chain. n Carry chain analysis must consider transistor, wiring delay. n Modern VLSI favors adder designs which have compact carry chains.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Full adder n Computes one-bit sum, carry: –s i = a i XOR b i XOR c i –c i+1 = a i b i + a i c i + b i c i n Ripple-carry adder: n-bit adder built from full adders. n Delay of ripple-carry adder goes through all carry bits.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Carry-lookahead adder n First compute carry propagate, generate: –P i = a i + b i –G i = a i b i n Compute sum and carry from P and G: –s i = c i XOR P i XOR G i –c i+1 = G i + P i c i

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Carry-lookahead expansion n Can recursively expand carry formula: –c i+1 = G i + P i (G i-1 + P i-1 c i-1 ) –c i+1 = G i + P i G i-1 + P i P i-1 (G i-2 + P i-1 c i-2 ) n Expanded formula does not depend on intermerdiate carries. n Allows carry for each bit to be computed independently.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Depth-4 carry-lookahead

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Analysis n Deepest carry expansion requires gates with large fanin: large, slow. n Carry-lookahead unit requires complex wiring between adders and lookahead unit—values must be routed back from lookahead unit to adder. n Layout is even more complex with multiple levels of lookahead.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Carry-skip adder n Looks for cases in which carry out of a set of bits is identical to carry in. n Typically organized into m-bit stages. n If a i = b i for every bit in stage, then bypass gate sends stage’s carry input directly to carry output.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Two-bit carry-skip structure

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Carry-select adder n Computes two results in parallel, each for different carry input assumptions. n Uses actual carry in to select correct result. n Reduces delay to multiplexer.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Carry-select structure

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Manchester carry chain n Precharged carry chain which uses P and G signals. n Propagate signal connects adjacent carry bits. n Generate signal discharges carry bit. n Worst-case discharge path goes through entire carry chain.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Manchester carry chain circuit

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Serial adder n May be used in signal-processing arithmetic where fast computation is important but latency is unimportant. n Data format (LSB first): 0110 LSB

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Serial adder structure LSB control signal clears the carry shift register:

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf ALUs n ALU computes a variety of logical and arithmetic functions based on opcode. n May offer complete set of functions of two variables or a subset. n ALU built around adder, since carry chain determines delay.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Mux-based ALU