1/14 Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-addressable Memory Using Gate- Block Selection Algorithm.

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Presentation transcript:

1/14 Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-addressable Memory Using Gate- Block Selection Algorithm Jui-Yuan Hsieh and Shanq-Jang Ruan, Department of Electronic Engineering National Taiwan University of Science and Technology, 2008 IEEE Presenter: Cheng-Yeh Tsao

2/14 Outline Previous work and observation PB-CAM architecture 1’s count PB-CAM 15-bit parameter extractor of the 1’s count PB-CAM Block-XOR PB-CAM The number of data related to the same parameter and average probability for the 1’s count and the block-xor approaches Proposed approach Truth table and average number of comparison operations of basic logic gates for a 2-bit skew data Gate-block selection algorithm An example Experimental results Conclusions

3/14 PB-CAM architecture Memory organization of the PB-CAM. During the writing phase During the data searching operation

4/14 1’s count PB-CAM Conceptual view of the 1’s count PB-CAM.

5/14 15-bit parameter extractor of the 1’s count PB-CAM

6/14 Block-XOR PB-CAM 15–bit parameter extractor of the block–xor PB-CAM. The number of blocks is = 1 = 0

7/14 The number of data related to the same parameter and average probability for the 1’s count and the block-xor approaches 88% 4 x 8 x 8 x / (2048 x 16)

8/14 Proposed approach n-bit block diagram of the proposed parameter extractor architecture. N / 8 log 2 8

9/14 Truth table and average number of comparison operations of basic logic gates for a 2-bit skew data C avg = N 0 (1 - p)+ N 1 ． p =

10/14 Gate-block selection algorithm AND OR XOR NAND NOR NXOR NAND NOR XOR ( C avg ： The average of comparison operations)

11/14 An example (1/4) N 0 = 8N 1 = 8

12/14 An example (2/4) N 0 = 7N 1 = 9

13/14 An example (3/4) N 0 = 9N 1 = 7

14/14 An example (4/4)

15/14 Experimental results (1/2)

16/14 Experimental results (2/2) LG ： Logic Gate FA ： Full Adder

17/14 Conclusions Gate-block selection algorithm Saving the power by reducing the number of comparison operations Computing parameter bits only use three logic gate

18/14 END