LOGIC CIRCUIT IMPLEMENTATION By Dr. Amin Danial Asham

References Digital Design 5th Edition, Morris Mano

Two graphic Symbols for NAND Gates Logic Circuit Implementation Practically NAND and NOR gate are easier to fabricate, therefore, logic circuit are commonly built using NAND and NOR rather than AND, OR, and NOT. The function of AND, OR, and NOT can be implemented using NOR gate. Noting that NOT gate is a single input NAND. The two-level implementation of Boolean functions with NAND gates requires that the functions be in sum-of-products form Two graphic Symbols for NAND Gates

To Convert to NAND implementation Two Level Implementation- NAND Gates Example: 𝐹=𝐴𝐵+𝐶𝐷 1-Each AND is replaced with NAND 2-Each OR is replaced with Invert- OR gate To Convert to NAND implementation 3-Check that the inverting circles cancels each other on the same line. If there is an inverter not cancelled, an inverter must be added on the same line or inverting the input literal. 𝐹=𝐴𝐵+𝐶𝐷 𝐴𝐵 𝐶𝐷 (𝐴𝐵)′ (𝐶𝐷)′ 𝐹= 𝐴𝐵 ′ ′ + 𝐶𝐷 ′ ′ =𝐴𝐵+𝐶𝐷 (𝐴𝐵)′ (𝐶𝐷)′ 𝐹= 𝐴𝐵 ′ 𝐶𝐷 ′ ′ =𝐴𝐵+𝐶𝐷

Two Level Implementation-NAND Gates (continue) Example: implement using NAND gates 𝐹 𝑥,𝑦,𝑧 = (1,2,3,4,5,7) Solution 𝐹 = 𝑥 𝑦 ′ ′ 𝑥 ′ 𝑦 ′ 𝑧 ′ ′ =𝑥 𝑦 ′ + 𝑥 ′ 𝑦+𝑧 𝑥𝑦′ 𝑥′𝑦 𝐹 = 𝑥 𝑦 ′ ′ + 𝑥 ′ 𝑦 ′ + 𝑧 ′ ′ =𝑥 𝑦 ′ + 𝑥 ′ 𝑦+𝑧 𝑥𝑦′ 𝑥′𝑦 𝑧′

Multilevel Implementation- NAND Gates Example: 𝐹=𝐴 𝐶𝐷+𝐵 +𝐵𝐶′

Two graphic Symbols for NOR Gates V. Logic Circuit Implementation – NOR Gates NOR operation is the dual of the NAND operation. The function of AND, OR, and NOT can be implemented using NOR gate. Noting that NOT gate is a single input NAND. A two-level implementation with NOR gates requires that the function be simplified into product-of-sums form Two graphic Symbols for NOR Gates

To Convert to NOR implementation V. Logic Circuit Implementation – NOR Gates (continue) Example: 𝐹=(𝐴 𝐵 ′ + 𝐴 ′ 𝐵)(𝐶+ 𝐷 ′ ) To Convert to NOR implementation 1-Each OR is replaced with NOR 2-Each AND is replaced with Invert- AND gate 3-Check that the inverting circles cancels each other on the same line. If there is an inverter not cancelled, an inverter must be added on the same line or inverting the input literal.

V. Logic Circuit Implementation – NOR Gates (continue) Example: Find the two level NOR implementation of a function expressed as a product of sums: 𝐹 = (𝐴 + 𝐵)(𝐶 + 𝐷)𝐸 Solution: 𝐸

VI. Other Two Level Forms SOP is implemented directly using AND-OR form and POS is implemented using OR- AND form, where the first gate is used in the first level and the second gate is a single gate in the second level. AND-OR and OR-AND can be converted to NOR –NOR or NAND-NAND. There are other forms of two level implementation: AND-NOR and NAND-AND, which are equivalent and both perform AND-OR- Invert. Example: 𝐹=(𝐴𝐵+𝐶𝐷+𝐸)′

VI. Other Two Level Forms (continue) OR-NAND and NOR-OR, which are equivalent and both perform OR-AND-Invert Example:𝐹=[ 𝐴+𝐵 𝐶+𝐷 𝐸]′

VI. Other Two Level Forms (continue) Because of the INVERT part in each case, it is convenient to use the simplification of 𝐹′(the complement) of the function.

VI. Other Two Level Forms (continue) Example: implement the function shown in the K-map in AND-NOR, NAND-AND, OR-NAND, and NOR-OR

𝑥⨁𝑦= 𝑥 ′ 𝑦+𝑥𝑦′ VII. XOR Gate 𝒙( 𝒙 ′ + 𝒚 ′ ) 𝒙𝒚 ′ =( 𝒙 ′ + 𝒚 ′ ) 𝒙𝒚 ′ =( 𝒙 ′ + 𝒚 ′ ) 𝒙( 𝒙 ′ + 𝒚 ′ ) 𝒚( 𝒙 ′ + 𝒚 ′ )

VII. XOR Gate (continue) XNOR is the complement of XOR, therefore: XNOR gives one in case of even number of 1’s in the input binary number.

VII. XOR Gate (continue) The Boolean expression for 3 inputs XOR is: (Odd number of 1’s)

VII. XOR Gate (continue) Logic Diagrams of Odd and Even functions

𝑷=𝒙⨁𝒚⨁𝒛 VIII. Parity Generation and Checking As an example, consider a three-bit message to be transmitted together with an even-parity bit. This Parity bit is transmitted with message to make the total number of ones in the message is even. 𝑷=𝒙⨁𝒚⨁𝒛

𝑪=𝒙⨁𝒚⨁𝒛⨁𝑷 VIII. Parity Generation and Checking (continue) On the receiver side the checker gives 0 if the number of 1’s is even, which means it is error free message. 𝑪=𝒙⨁𝒚⨁𝒛⨁𝑷

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