CPE432 Chapter 4B.1Dr. W. Abu-Sufah, UJ Chapter 4B: The Processor, Part B-2 Read Section 4.7 Adapted from Slides by Prof. Mary Jane Irwin, Penn State University And Slides Supplied by the textbook publisher

CPE432 Chapter 4B.2Dr. W. Abu-Sufah, UJ Memory-to-Memory Copies Data Hazard ALU IM Reg DMReg I n s t r. O r d e r 1 lw $1,4($2) 2 sw $1,4($3) ALU IM Reg DMReg  load immediately followed by store (memory-to-memory copy)  What could be done? CC0CC1CC2CC3CC4 CC5 CC6CC7CC8 The Data Hazard: Instruction 1 loads register 1 in clock cycle 4 instruction 2 needs the NEW data of register 1 during clock cycle 2

CPE432 Chapter 4B.3Dr. W. Abu-Sufah, UJ Memory-to-Memory Copies Data Hazard ALU IM Reg DMReg I n s t r. O r d e r 1 lw $1,4($2) 2 sw $1,4($3) ALU IM Reg DMReg  Can fix data hazard by waiting – stalling CC0CC1CC2CC3CC4 CC5 CC6CC7CC8 stall Instruction 1 writes data in register 1 in first half of cycle 4 instruction 2 reads data from register 1 in second half of cycle 4 The data hazard is resolved! (BUT impacts CPI)

CPE432 Chapter 4B.4Dr. W. Abu-Sufah, UJ Memory-to-Memory Copies I n s t r. O r d e r lw $1,4($2) ALU IM Reg DMReg sw $1,4($3) ALU IM Reg DMReg  For loads immediately followed by stores (memory-to- memory copies) can avoid a stall by adding forwarding hardware from the MEM/WB register to the data memory input. l Would need to add a Forward Unit and a mux to the MEM stage CC0CC1CC2CC3CC4 CC5 CC6CC7CC8

CPE432 Chapter 4B.5Dr. W. Abu-Sufah, UJ Add-to-store hazard I n s t r. O r d e r add $1, ALU IM Reg DMReg sw $1,4($3) ALU IM Reg DMReg  What if lw was replaced with add $1, - is forwarding still needed? From where, to where? CC0CC1CC2CC3CC4 CC5 CC6CC7CC8

CPE432 Chapter 4B.6Dr. W. Abu-Sufah, UJ Forwarding with Load-use Data Hazards I n s t r. O r d e r lw $1,4($2) and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DM ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg sub $4,$1,$5 CC0CC1CC2CC3CC4 CC5 CC6CC7CC8

CPE432 Chapter 4B.7Dr. W. Abu-Sufah, UJ stall Forwarding with Load-use Data Hazards I n s t r. O r d e r lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9 ALU IM Reg DMReg ALU IM Reg DM ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg ALU IM Reg DMReg sub $4,$1,$5 and $6,$1,$7 xor $4,$1,$5 or $8,$1,$9  Will still need one stall cycle even with forwarding CC0CC1CC2CC3CC4 CC5 CC6CC7CC8 Before stalling, when lw instruction was in the EX stage, the Use instructionn was in the ID stage

CPE432 Chapter 4B.8Dr. W. Abu-Sufah, UJ Load-use Hazard Detection Unit  Need a Hazard Detection Unit in the ID stage that inserts a stall between the load and its use 1.ID Hazard Detection Unit: if (ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))) stall the pipeline  The first line tests to see if the instruction now in the EX stage is a lw ; the next two lines check to see if the target register of the lw ( ID/EX.RegisterRt ) matches either Rs or Rt register of the instruction in the ID stage (the load-use instruction)  After this one cycle stall, the forwarding logic can handle the remaining data hazards When lw instruction is in the EX stage, the load-use instruction is in the ID stage

CPE432 Chapter 4B.9Dr. W. Abu-Sufah, UJ Hazard (Detection)/Stall Hardware  Along with the ID Hazard Detection Unit, we have to implement the stall. This means:  Prevent the instructions in the IF and ID stages from progressing down the pipeline – done by preventing the PC register and the IF/ID pipeline register from changing The ID Hazard Detection Unit controls the writing of the PC and IF/ID registers through the use of the signals ( PC.write ) ( IF/ID.write )  Insert a “bubble” between the lw instruction (in the EX stage) and the “load-use” instruction (in the ID stage) (i.e., insert a noop in the execution stream) Set the control bits in the EX, MEM, and WB control fields of the ID/EX pipeline register to 0 ( noop ). The ID Hazard Unit controls the mux that chooses between the real control values and the 0’s.

CPE432 Chapter 4B.10Dr. W. Abu-Sufah, UJ Hazard (Detection)/Stall Hardware (cont.)  Let the lw instruction and the instructions after it in the pipeline (before it in the code) proceed normally down the pipeline

CPE432 Chapter 4B.11Dr. W. Abu-Sufah, UJ Adding the Hazard/Stall Hardware Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl Branch PCSrc Forward Unit Hazard Unit 0 1

CPE432 Chapter 4B.12Dr. W. Abu-Sufah, UJ Adding the Hazard/Stall Hardware Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data ALU Shift left 2 Add Data Memory Address Write Data Read Data IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control ALU cntrl Branch PCSrc Forward Unit Hazard Unit 0 1 ID/EX.RegisterRt 0 ID/EX.MemRead PC.Write IF/ID.Write IF/ID.RegisterRs and IF/ID.RegisterRt