Introduction to FPGA Development Justin Thiel Two Sigma Investments

clk) begin r_x <= x; if (x) r_y <= r_x; end xr_x r_y clk Flip Flop Flip Flop Mapping Operations to HW

What is Inside an FPGA?

abcCarry Out a + b = c LUT Inputs (Address) LUT Outputs (Data)

What is Inside an FPGA?

module ttl74163 #( parameter WIDTH = 4 ) ( input clk, input rst_n, input [WIDTH-1:0] i_load_cnt, input i_load_n, input i_cnt_en, input i_cnt_en_w_carry_out, output [WIDTH-1:0] o_cnt, output o_carry_out ); // Some sweet logic here... endmodule

Exercise Binary Counter Simulation

Verilog Primer

Verilog Numerical Types Format: [WIDTH]’[BASE][VALUE] 2’d0 -> 2 bit decimal 0 2’b0 -> 2 bit binary 0 4’he -> 4 bit hexadecimal 14 4’o7 -> 4 bit octal 7 Arbitary bit widths are allowed Hex (h), Binary (b), Decimal (d), and octal (o) bases are handled Same numeric form is used for everything (no floats, doubles, etc..) For “signed” integers logic tends to use 2s complement format

Verilog Operators Bitwise: OR: 3’b010 | 3’b100 -> 3’h110 AND: 3’b100 & 3’b111 -> 3’b100 XOR: 3’b101 ^ 3’b110 -> 3’b011 NOT: ~3’b101 -> 3’b010 Arithmetic: Addition : 3’b ’b100 -> 3’b110 Subtraction: 3’b100 – 3’b001 -> 3’b011 Comparators: Greater Than: (3’b100 > 3’b011) -> 1’b1 Equality : (3’b100 == 3’b010) -> 1’b0 Inequality : (3’b100 != 3’b000) -> 1’b1

Verilog Concepts wire w_rst; assign w_rst = ~rst_n; wires are used to define “stateless” signals They can only be assigned to by a (single) assign statement The value of a wire changes whenever the inputs to it’s assign statement transition clk rst_n w_rst rst_n

Verilog Concepts reg r_en_a; clk) begin r_en_a <= i_en_a; end regs are used to define “stateful” signals. They should only be assigned to within a (single) always block The value of a reg changes only when its always block evaluates Flip Flop r_en_a i_en_a clk i_en_a r_en_a

Verilog Concepts reg r_en_a; reg r_en_b; clk) begin r_en_a <= i_en_a; r_en_b <= r_en_a; end All statements in an always block evaluate in parallel. Flip Flop r_en_ai_en_a clk i_en_a r_en_a r_en_b Flip Flop r_en_b clk

Verilog Concepts reg r_en_a; reg r_en_b; clk) begin r_en_a <= i_en_a; end clk) begin r_en_b <= r_en_a; end All always blocks execute in parallel. Flip Flop r_en_ai_en_a clk i_en_a r_en_a r_en_b Flip Flop r_en_b clk

Verilog Concepts reg r_rst; begin r_rst <= ~rst_n; End..Same as... begin r_rst <= ~rst_n; end always blocks are not required to be clocked Making a block sensitive to ‘ * ’ causes it to evaluate whenever a right-hand side value changes clk rst_n r_rst rst_n

Dealing with Bits // 1 bit wire Wire w_rst; // 4 bit register reg [3:0] r_cnt; // 1024 bit wire wire [1023:0] x; // 4x 32b registers reg [31:0] r_data [3:0]; // 4x4x 32b registers reg [31:0] r_data2d [3:0][3:0]; Brackets ‘[]’ are used to denote multi-bit fields

Dealing with Bits wire [3:0] x; wire y; wire [1:0] z; // Set y to Bit 0 of x assign y = x[0]; // Set z to Bits 1:0 of x assign z = x[1:0]; Brackets ‘[…]’ are also used to bit slice vectors. Use ‘:’ to specify a range. x[1] x[0] y z[1] z[0]

Dealing with Bits wire [3:0] x [1:0]; wire [3:0] y; wire [3:0] z; // Pulling Array Entries assign x[0] = y; assign x[1] = z; Brackets ‘[…]’ are also used to index into arrays z y x[0] x[1]

Dealing with Bits wire [1:0] x; wire y; wire z; // Set x[1] to y, x[0] to z of y and z assign x = {y,z}; Use curly braces ‘ {…} ’ to concatenate bit vectors z y x[1] x[0]

Module Declaration and Port Maps module ttl74163 #( parameter WIDTH = 4 ) ( // Clock and Reset Pins input clk, input rst_n, // Inputs input [WIDTH-1:0] i_load_cnt, input i_load_n,... // Outputs output [WIDTH-1:0] o_cnt, output o_carry_out ); All designs start with a module declaration

Module Declaration and Port Maps module ttl74163 #( parameter WIDTH = 4 ) ( // Clock and Reset Pins input clk, input rst_n, // Inputs input [WIDTH-1:0] i_load_cnt, input i_load_n,... // Outputs output [WIDTH-1:0] o_cnt, output o_carry_out ); parameters can be used to create logic which is configurable at compile (synthesis) time They must be enclosed within a “ #( … ) ” block

Module Declaration and Port Maps module ttl74163 #( parameter WIDTH = 4 ) ( // Clock and Reset Pins input clk, input rst_n, // Inputs input [WIDTH-1:0] i_load_cnt, input i_load_n,... // Outputs output [WIDTH-1:0] o_cnt, output o_carry_out ); Inputs denote signals which are driven outside the module Outputs denote signals which are driven by the module These signals form the portmap and are enclosed in a “ (…) ” block ttl74163 i_load_cnt i_load_n o_cnt o_carry_out

Module Instantiation parameter MY_WIDTH = 4; wire [MY_WIDTH-1:0] w_load_cnt; wire w_load_n; wire [MY_WIDTH-1:0] w_cnt; wire w_carry_out; ttl74163 #(.WIDTH (MY_WIDTH) ) my_ttl_counter (.clk (clk),.rst_n (rst_n),.i_load_cnt (w_load_cnt),.i_load_n (w_load_n),....o_cnt (w_cnt),.o_carry_out (w_carry_out)); Inputs and Outputs should be connected to wires/regs. Each instance represents a unique copy of the logic defined in the module a given module is a unique copy of the logic my_ttl_counter w_load_cnt w_load_n w_cnt w_carry_out

Verilog Constructs reg [3:0] r_cnt; wire [3:0] w_cnt; clk) begin // Clear if (rst) r_cnt <= '0; else r_cnt <= w_cnt; end Simple if..else blocks synthesize as a 2- to-1-mux This construct can only be used in an always block. 4’d0 w_cnt rst Flip Flop r_cnt clk 1 0

Verilog Constructs reg r_set; clk) begin r_set <= (rst) ? 0 : i_set; end... wire w_set; assign w_set = (rst) ? 0 : i_set; Ternary operators ( ? ) also imply a 2-to-1 mux Can be used in always blocks or assign statements. 1’b0 i_set rst w_set Flip Flop r_set clk 1 0

Verilog Constructs reg [1:0] r_cnt; wire w_a, w_b; clk) begin case ({w_a, w_b}): 2’b01: r_cnt <= 2’d1; 2’b10: r_cnt <= 2’d1; 2’b00: r_cnt <= 2’d0; 2’b11: r_cnt <= 2’d2; default: r_cnt <= 2’d0; endcase end case statements will (generally) imply an n-to- 1 mux This construct can only be used in an always block. default case is a failsafe, provide for best results 2’b00 2’b01 {w_a, w_b} 2’b10 2’b11 Flip Flop r_cnt clk

Verilog Constructs reg [1:0] r_cnt; wire w_en; clk) begin if (w_en) r_cnt <= r_cnt + 1; else r_cnt <= r_cnt; end Arithmetic operations synthesize into physical representations thereof 2’d1 2x Flip Flops r_cnt w_en 2 bit Adder 1 0 clk

Verilog Constructs // Full Adder Example module full_adder( input i_a, input i_b, input i_cin, output o_sum, output o_cout ); wire w_tmp; assign w_tmp = (i_a ^ i_b); assign o_sum = (w_tmp ^ i_cin); assign o_cout= (i_a & i_b) | (i_cin & w_tmp); endmodule; You can also build arithmetic operators yourself… abCiSCo

Verilog Constructs reg [3:0] r_cnt; clk) begin // Clear if (w_rst) r_cnt <= '0; // Load value else if (w_load) r_cnt <= i_cnt; // Count else if (w_cnt_en) r_cnt <= r_cnt + 1; else r_cnt <= r_cnt; end if..else if...else blocks imply priority just as they do in a C/C++. In this case, w_rst takes priority, followed by w_load and so on…

Verilog Constructs 4x Flip Flops w_rst 4’d0 w_load i_cnt w_cnt_en 4 bit Full Adder 4’d1 r_cnt clk) begin if (w_rst) r_cnt <= '0; else if (w_load) r_cnt <= i_cnt;... else if (w_cnt_en) r_cnt <= r_cnt + 1; else r_cnt <= r_cnt; end clk

Syntactic Sugar wire [3:0] x; wire [3:0] y; wire [3:0] z; assign x = ‘0; assign y = ‘1; assign z = (x == ‘1) ? x : y; ‘0 = “all bits set to zero” ‘1 = “all bits set to one”

Summary Use wires for purely combinatorial logic and regs for anything stateful A reg does not always imply a flip flop Simple If…Else and Ternary statements synthesize into 2-to-1 muxes Chains of If…Else If…Else blocks can lead to long timing paths A case statement will yield an n-to-1 mux when coded properly

Questions

Exercise 2 Binary Counter Modification

clk i_en o_cnt 12 … … … Exercise 2 - Hint clk r_cnt_dn o_cnt 12 … … clk r_cnt_dn o_cnt 12 … … … Wrong Correct

Exercise 3 FPGA build flow