EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. EE5900 Advanced Algorithms for Robust VLSI CAD

EE141 © Digital Integrated Circuits 2nd Manufacturing 2 Silicon Wafer Single die Wafer From Going up to 12” (30cm)

EE141 © Digital Integrated Circuits 2nd Manufacturing 3 N-Well Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 4 Dual-Well Process Dual-Well Trench-Isolated CMOS Process Transistors at bottom Wires on the top

EE141 © Digital Integrated Circuits 2nd Manufacturing 5 Circuit Under Design

EE141 © Digital Integrated Circuits 2nd Manufacturing 6 Its Layout View

EE141 © Digital Integrated Circuits 2nd Manufacturing 7 7 VLSI Design and Fabrication Lithography Process Designed Chip Layout Fabricated Chip

EE141 © Digital Integrated Circuits 2nd Manufacturing 8 Chip

EE141 © Digital Integrated Circuits 2nd Manufacturing 9 9 Lithography System - Simple View Illumination source Mask Objective Lens Aperture Wafer

EE141 © Digital Integrated Circuits 2nd Manufacturing 10 Photo-Lithography Process – Full View oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Part of layout

EE141 © Digital Integrated Circuits 2nd Manufacturing 11 An Example: Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

EE141 © Digital Integrated Circuits 2nd Manufacturing Manufacturing Process 12  Part of the layout is put on a mask (level), so we have many masks.  Each mask level corresponds to different actions in the fabrication process  Each mask level contains non-overlapping polygons, but polygons from different masks may overlap subject to max/min distance rules

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example 13 A set of masks

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - I 14

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - II 15

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - III 16

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - IV 17

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - V 18

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - VI 19 Active (diffusion) contact

EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - VII 20

EE141 © Digital Integrated Circuits 2nd Manufacturing 21 General CMOS Process Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

EE141 © Digital Integrated Circuits 2nd Manufacturing 22 Contact and Via  Contact:  link metal with diffusion (active)  Link metal with gate poly  Via:  Link wire with wire  Overlapping two layers (diffusion, gate poly or metal) and providing a contact hole filled with metal  Substrate Contact and Well Contact:  Link substrate or well to supply voltage

EE141 © Digital Integrated Circuits 2nd Manufacturing 23 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer (extended layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

EE141 © Digital Integrated Circuits 2nd Manufacturing 24 CMOS Process Walk-Through SiO (field oxide) 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well implants (by adjusting well doping in order to have more donar impurities such as phosphorus) n (f) After p-well implants (by adjusting well doping in order to have more acceptor impurities such as boron) p This implant will only impact the area below the gate oxide but not gate oxide itself

EE141 © Digital Integrated Circuits 2nd Manufacturing 25 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

EE141 © Digital Integrated Circuits 2nd Manufacturing 26 CMOS Process Walk-Through Interlayer dielectric (between wire and diffusion, between wire and wire)

EE141 © Digital Integrated Circuits 2nd Manufacturing 27 CMOS Polysilicon Aluminum

EE141 © Digital Integrated Circuits 2nd Manufacturing 28 Metal

EE141 © Digital Integrated Circuits 2nd Manufacturing 29 Challenge Illumination source Mask Objective Lens Aperture Wafer 193nm 45nm

EE141 © Digital Integrated Circuits 2nd Manufacturing 30 Mask v.s. Printing 0.25µ0.18µ 0.13µ 90-nm65-nm Layout What you design is NOT what you get!

EE141 © Digital Integrated Circuits 2nd Manufacturing 31 Motivation  Chip design cannot be fabricated  Gap –Lithography technology: 193nm wavelength –VLSI technology: 45nm features  Lithography induced variations –Impact on timing and power l Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported. Technology node 130nm90nm65nm45nm Gate length (nm) Tolerable variation (nm) Wavelength (nm)

EE141 © Digital Integrated Circuits 2nd Manufacturing 32 Gap: Lithography Tech. v.s. VLSI Tech. 193nm 28nm, tolerable distortion: 2nm Increasing gap  Printability problem (and thus variations) more severe!