VHDL for Combinational Circuits. VHDL We Know Simple assignment statements –f <= (NOT x1 AND NOT x2) OR x1;

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Presentation transcript:

VHDL for Combinational Circuits

VHDL We Know Simple assignment statements –f <= (NOT x1 AND NOT x2) OR x1;

Assignment Statements Selected signal assignments Conditional signal assignments Generate statements If-then-else statements Case statements

WITH s SELECT f <=w0 WHEN '0', w1 WHEN OTHERS ; Selected Signal Assignments Use of OTHERS instead of ‘1’ is required because VHDL specifies that a WHEN clause must be included for every possible value of the selection input signal s. s is STD_LOGIC type so it can take on values 0, 1, Z, -, and others (see Brown section 4.12).

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT (w0, w1, s: IN STD_LOGIC ; f: OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN WITH s SELECT f <=w0 WHEN '0', w1 WHEN OTHERS ; END Behavior ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT (w0, w1, w2, w3: IN STD_LOGIC ; s: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f: OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ; Because s is a vector “”s instead of ‘’s must be used in select statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Behavior ;

Conditional Signal Assignments f <= w0 WHEN s = '0' ELSE w1 ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT (w0, w1, s : INSTD_LOGIC ; f : OUTSTD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END Behavior ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT (w: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z: OUT STD_LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS BEGIN y <="11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ; d w 0 y 1 d y z 1 x x 0 x w x 0 x w x w

Number Comparison USE ieee.std_logic_unsigned.all ; A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB <='1' WHEN A = B ELSE '0' ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT (A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB: OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <='1' WHEN A = B ELSE '0' ; AgtB B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; --vs USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT (A, B: IN SIGNED(3 DOWNTO 0) ; -- vs STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB: OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ; Same comparator with signed number

--16-to-1 Multiplexer from 5 4-to-1 Multiplexers LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY work ; USE work.mux4to1_package.all ; ENTITY mux16to1 IS PORT (w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux16to1 ; ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

Generate Statement G1:FOR i IN 0 TO 3 GENERATE END GENERATE Generate must have a label Iteration variable isn’t declared

BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.mux4to1_package.all ; ENTITY mux16to1 IS PORT (w: IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux16to1 ; ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

IF-THEN-ELSE PROCESS ( w0, w1, s ) BEGIN IF s = '0' THEN f <= w0 ; ELSE f <= w1 ; END IF ; END PROCESS ; If-then-else must be inside PROCESS statement Sensitivity list

PROCESS Statement When there is a change in the value of any signal in the process’s sensitivity list, then the process becomes active. Once active, the statements inside the process are evaluated in sequential order. Any assignments made to signals inside the process are not visible outside the process until all of the statements in the process have been evaluated. If there are multiple assignments to the same signal, only the last one has any visible effect.

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT (w0, w1, s: IN STD_LOGIC ; f: OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN IF s = '0' THEN f <= w0 ; ELSE f <= w1 ; END IF ; END PROCESS ; END Behavior ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s: IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN f <= w0 ; IF s = '1' THEN f <= w1 ; END IF ; END PROCESS ; END Behavior ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z: OUT STD_LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS BEGIN PROCESS ( w ) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = '1' THEN y <= "01" ; ELSE y <= "00" ; END IF ; END PROCESS ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z: OUT STD_LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS BEGIN PROCESS ( w ) BEGIN y <= "00" ; IF w(1) = '1' THEN y <= "01" ; END IF ; IF w(2) = '1' THEN y <= "10" ; END IF ; IF w(3) = '1' THEN y <= "11" ; END IF ; z <= '1' ; IF w = "0000" THEN z <= '0' ; END IF ; END PROCESS ; END Behavior ;

CASE Statement PROCESS ( w0, w1, s ) BEGIN CASE s IS WHEN '0' => f <= w0 ; WHEN OTHERS => f <= w1 ; END CASE ; END PROCESS ;

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y: OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS BEGIN PROCESS ( w, En ) BEGIN IF En = '1' THEN CASE w IS WHEN "00" => y <= "1000" ; WHEN "01" => y <= "0100" ; WHEN "10" => y <= "0010" ; WHEN OTHERS =>y <= "0001" ; END CASE ; ELSE y <= "0000" ; END IF ; END PROCESS ; END Behavior ;