Chapter 11Chapter 12 Memory system designI/O system design Objectives: The importance of bus buffering How the 8088 addresses (accesses) memory - I/O ports The design of custom memory and I/O address decoders The difference between full and partial address decoding How wait states may be inserted into memory and I/O read/write cycles The difference between static and dynamic RAMs How a dynamic RAM is addressed and what purpose refresh cycles serve The operation of buffered input ports The operation of latched output ports Parallel I/O with the 8255 PPI Serial I/O with the 8251 UART EE314 Microprocessor Systems Based on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos

11.3 Bus Buffering 8282 STB OE D Q LE Memory Address Decoder Memory Chip 1 Memory Chip 2 Memory Chip n Data Bus Address Bus 8286 OE T 8282 STB OE D Q LE RD WR IO/M A16/S3-A19/S6 A8-A AD0-AD7 ALE DEN DT/R READY 74LS244 G1 G2 CE (Chip Enable) or CS (Chip Select), activate each chip WR and RD for each chip some high Address lines and IO/M used to identify the accessed chip the decoder drives READY: provides enough access time for the selected chip some low address lines identify the internal accessed byte (more for memory, few for I/O) I/O Address Decoder I/O Chip 1 I/O Chip 2 I/O Chip m

A0-A13 16KB EPROM chip OE FFFFF Full address decoding Memory Map - WR RD A19, A18 assigned to 00 => CS active for every address from to 3FFFF A18 = 0 A19 = 0 IO/M = 0 IO/M = 0 => Memory map A0... A17 256KB RAM chip A18 A19 CS1’ MWTC MRDC The same Memory-map assignment CS1 A18 A19 IO/M A7 B6 C5 74LS E12 E21 E0 A17 A18 A19 A14 A15 A16 A19 = 1, A18 = 0, A17 = 0 activate the decoder A16, A15, A14 select one EPROM chip A14 A15 A16 A17 A18 A19 CS2 A19=A18=...=A14=1 select the EPROM All the address lines used by the decoder or memory chip => each byte is uniquely addressed = full address decoding FFFFF 3FFFF FFFFF FC000 3FFFF FFFFF FC000 83FFF FFFF FFFFF FC000 9FFFF 9C000 83FFF FFFF Memory Map 2 20 = 1,048,576 different byte addresses = 1Mbyte MRDC A0... A17 256KB RAM chip WR RD A 256Kbyte = 2 18 RAM chip has 18 address lines, A0 - A17 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip CS4 CS5 CS6 CS7 CS8 CS9 CS10 16KB EPROM chip OE CS3 A0-A13

FFFFF Partial address decoding Memory Map - WR RD A0... A15 64KB RAM chip A18 A19 CS1’ MWTC MRDC The same Memory-map assignment CS1 A18 A19 IO/M Some address lines not used by the decoder or memory chip => mirror images = partial address decoding FFFFF 3FFFF FFFFF 3FFFF FFFF FFFF FFFF FFFFF FC000 7FFFF 7C000 3FFFF FFFF FFFF FFFF Memory Map A0... A15 64KB RAM chip WR RD A 64Kbyte = 2 16 RAM chip has 16 address lines, A0 - A15 FFFFF FC000 9FFFF 9C000 83FFF FFFF 7C000 3FFFF FFFF FFFF FFFF FFFFF FC000 DFFFF DC000 CF000 CC000 9FFFF 9C000 83FFF FFFF 7C000 3FFFF FFFF FFFF FFFF base image mirror images MRDC A0-A13 16KB EPROM chip OE A14 A15 A16 A17 A18 CS2 A18=...=A14=1 select the EPROM mirror image base image mirror image A19, A18 assigned to 00 => CS active for every address from to 3FFFF A18 = 0 A19 = 0 IO/M = 0 IO/M = 0 => Memory map A16, A17 not used => four images for the same chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip 16KB EPROM chip CS4 CS5 CS6 CS7 CS8 CS9 CS10 16KB EPROM chip OE CS3 A0-A13 A7 B6 C5 74LS E12 E21 E0 A17 A19 A14 A15 A16 A19 = 1, A17 = 0 activate the decoder A16, A15, A14 select one EPROM chip

FFFF 0000 Full address decoding I/O Map - All A15...A0 used by the decoder or I/O chip => each byte is uniquely addressed = full address decoding FFFF FFFC 0000 FFFF FFFC A7 B6 C5 74LS E12 E21 E0 A15 A0 A1 A2 A15=1,A14...A3= 0 activate the decoder for every address in range A2, A1, A0 select one input LATCH (port) IORC 1 byte input port 1 byte input port 1 byte input port 1 byte input port 1 byte input port 1 byte input port 1 byte input port CS4 CS5 CS6 CS7 CS8 CS9 CS10 1 byte input port OE CS3 A14... A I/O Map 2 16 = 65,536 different byte addresses =64Kbyte A2... A13 A14 A15 A0-A PPI WR RD CS2 A15=...=A2=1 select the 8255 chip IOWC IORC A0... A15 IO/M WR RD A15... A0 assigned to 0 => CS active only for 0000 address A0 = 0... A15 = 0 IO/M = 1 IO/M = 1 => I/O map 1 byte I/O port WR RD A0... A15 CS1’ IOWC IORC The same I/O-map assignment CS1 1 byte I/O port WR RD A 1byte I/O port no internal address decoding

FFFF 0000 FFFF 7 mirrors 0000 base Partial address decoding I/O Map - Some address lines not used by the decoder or I/O chip => mirror images = partial address decoding FFFF FFFC 7FFF 7FFC 7 mirrors 0000 base FFFF FFFC 800F mirror 800E base mirror 8000 base 7FFF 7FFC 7 mirrors 0000 base 8088 I/O Map 2 16 = 65,536 different byte addresses =64Kbyte A2... A12 A13 A14 A0-A PPI WR RD CS2 A14=...=A2=1 select the 8255 chip IOWC IORC base mirror A7 B6 C5 74LS E12 E21 E0 A15 A1 A2 A3 A15=1,A14...A4= 0 activate the decoder for every address in range F A3, A2, A1 select one input LATCH (port) IORC 1 byte input port 1 byte input port 1 byte input port 1 byte input port 1 byte input port 1 byte input port 1 byte input port CS4 CS5 CS6 CS7 CS8 CS9 CS10 1 byte input port OE CS3 A14... A4 A3... A15 IO/M WR RD A15... A3 assigned to 0 => CS active for every address in range A3 = 0... A15 = 0 IO/M = 1 IO/M = 1 => I/O map 1 byte I/O port WR RD A3... A15 CS1’ IOWC IORC The same I/O-map assignment CS1 1 byte I/O port WR RD A 1byte I/O port no internal address decoding