1 Lecture 9 Input/Output ITEC 1000 “Introduction to Information Technology”

2 Lecture Template: I/O Devices I/O Devices I/O Modules I/O Modules I/O Configurations I/O Configurations Types of I/O Types of I/O Polling and Interrupts in I/O Polling and Interrupts in I/O Types of Information Systems Types of Information Systems I/O System Architecture I/O System Architecture Interface Buses and Ports Interface Buses and Ports

3 I/O Considerations Speed Issues CPU operates at speeds much faster than the fastest I/O device Devices operate at different speeds Bursts of data Block data transfer required for some devices Coordination I/O devices completely operate under CPU program control Several devices perform I/O simultaneously Unexpected input (Ctrl-C, Ctrl-S, Ctrl-Alt-Del) Various input formats Status information needed for each device

4 Typical Data Rates of I/O Devices

5 I/O Device Interface Issues Different formats parallel interface serial interface Buffering of data Burst vs. stream Different control requirements electromechanical

6 Simple Configuration through I/O Module I/O device connected to the CPU through I/O module I/O module contains hardware providing: Block transfer Appropriate buffering Standardized interface to the CPU Control of the connected I/O device

7 I/O Module Functions Recognizes messages from device(s) addressed to it and accepts commands from the CPU Provides a buffer where the data from memory can be held until it can be transferred to the disk Provides the necessary registers and controls to perform a direct memory transfer Physically controls the device Copies data from its buffer to the device/from the CPU to its buffer Notifies with interrupts

8 I/O Configurations (1 of 2) CPU I/O module I/O device Keyboard Mouse Voice input (microphone) Scanner Voice output (speaker) Dot-matrix printer Laser printer Graphics display Local area network Optical disk Magnetic tape Magnetic disk Can take many forms, e.g., Device controller Disk controller

9 I/O Configurations (2 of 2) I/O device I/O module CPU I/O data I/O address I/O module I/O control

10 Bus view I/O device I/O module CPU I/O data I/O address I/O module I/O control Data bus Address bus Control bus

11 I/O vs. Memory How is I/O differentiated from memory? Two possibilities Memory-mapped I/O I/O-mapped I/O

12 Memory-Mapped I/O Memory and I/O… reside in different parts of the same “space” are accessed in the same manner Differentiated only by their addresses Example: STA address (store the contents of the accumulator at the specified address) STA 2000 might store A in memory STA 8000 might store A in an I/O device

13 Memory Map FFFF 0000 Memory I/O

14 I/O vs. Memory How is I/O differentiated from memory? Two possibilities Memory-mapped I/O I/O-mapped I/O

15 I/O-Mapped I/O Memory and I/O… Occupy different “spaces” Are accessed by unique instructions Differentiated by instructions Memory instructions Most instructions reference memory I/O instructions move data to/from a specified I/O address (“port”) and a CPU register (e.g., the accumulator) IN port – inputs data from a device OUT port – outputs data to a device

16 Memory Maps FFFF 0000 Memory I/O FFFF 0000

17 Implementation of I/O-Mapped I/O Typically, access to memory and I/O uses the same address bus and data bus A dedicated control bus signal differentiates a “memory cycle” from an “I/O cycle” On Intel’s Pentium CPU, this control bus signal is named M/IO M/IO = 0  memory cycle M/IO = 1  input/output cycle

18 M/IO One of the control bus signals is named M/IO I/O device CPU I/O data I/O address I/O module I/O control Data bus Address bus Control bus Memory

19 Types of I/O Programmed I/O Interrupt-driven I/O Direct memory access (DMA)

20 Programmed I/O (1 of 3) I/O module connected to a pair of I/O registers in CPU via bus Transfer: one word at a time Input: I/O device I/O module I/O register AR under program control Output: AR I/O register I/O module I/O device In practice: multiple I/O devices connected to CPU

21 Programmed I/O (2 of 3) I/O data and address registers in CPU: work similarly to MAR and MDR Address information must be sent with the I/O instruction in the address field Requires full instruction fetch/execute cycle for each word data transfer Very slow Primary use: keyboards communication with I/O modules to control I/O operations (see DMA)

22 Programmed I/O (3 of 3)

23 Programmed I/O: Example (1 of 2) Instruction register

24 Programmed I/O: Example (2 of 2)

25 Polling A form of programmed I/O, wherein device “status” is checked to determine if an I/O operation is needed E.g., A keyboard can be polled to determine if a key has been struck and a code is waiting to be read Useful when there are a lot of similar devices connected to one system (e.g., hundreds of terminals)

26 Types of I/O Programmed I/O Interrupt-driven I/O Direct memory access (DMA)

27 Interrupts Signal that causes the CPU to alter its normal flow of a program/instruction execution frees CPU from waiting for events provides control for external input Examples unexpected input abnormal situation illegal instructions multitasking, multiprocessing Provided by special control lines to CPU interrupt lines Called interrupt lines In modern PCs: up to 32 labeled IRQ0..IRQ31 interrupt Transmits message called interrupt Causes computer to suspend program execution and jump to interrupt processing program

28 Interrupt Terminology (1 of 2) Interrupt lines (hardware) Interrupt request Interrupt handlers Program that services the interrupt Also known as an interrupt routine Determines appropriate course of actions when interrupt occurs Process Control Block (PCB) stack Located in a part of memory known as the stack area All registers of a program (last instruction executed, data value in registers) are saved here before control is transferred to the interrupt handler

29 Interrupt Terminology (2 of 2) Servicing the interrupt suspends program in progress saves pertinent information including last instruction executed and data values in registers in the PCB (process control block) branches to interrupt handler (routine) After interrupt routine is complete, it returns control to the interrupted program, all original register values are restored

30 Servicing an Interrupt

31 Saving Registers For the interrupted program to resume, the CPU status and data registers must be saved (because they will change during the ISR) They are saved before the ISR executes They are restored after the ISR executes They are saved either On the stack (a special area of memory to temporarily hold information), or In a process control block (PCB)

32 Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator

33 Interrupts for External Events An interrupt signal occurs when an “external event” occurs in a device – an event that requires the CPU’s attention E.g., Keyboard: a key has been hit (the ISR reads the code for the key) Notebook computer cover: the cover is closed (the ISR puts the computer in standby mode)

34 Interrupts for External Events

35 Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator

36 Interrupts for Completion Signals An interrupt signal occurs when a device has completed an operation – and the CPU should know about it E.g., Printer: the output buffer is empty (the CPU can send more data) Scanner: a data transfer is complete (the CPU/application can proceed to process the image data)

37 Interrupts for Completion Signals

38 Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator

39 Interrupts for Allocating CPU Time Useful on multi-tasking systems – systems that can execute more than one program at a time E.g., A timer is programmed to interrupt the CPU every 100 µs (for example) The ISR is a “dispatcher program” Execution switches to another program (for 100 µs), etc.

40 Interrupts for Allocating CPU Time

41 Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator

42 Interrupts for Abnormal Events An interrupt signal occurs when an abnormal event occurs that needs immediate system attention E.g., A heat sensor near the CPU chip – if the temperature is too high, an interrupt is generated, the ISR activates the fan near the CPU chip

43 Multiple Interrupts In a real computer system Many I/O devices Multiple interrupts occur Identifying devices caused interrupt by: Polling (checking for input in rotation) Vectored interrupts (include address of interrupting device as part of the interrupt) Interrupt priorities Loss of data vs. task completion Maskable (disabled) interrupts

44 Vectored Interrupts

45 Polled Interrupts

46 Interrupt Priorities

47 Types of I/O Programmed I/O Interrupt-driven I/O Direct memory access (DMA)

48 Direct Memory Access Used for high-speed data transfers between an I/O device and memory in blocks During the transfer, the CPU is not involved Typical DMA devices: Disk drives, tape drives Remember (Table in slide 4) Keyboard data rate  0.01 KB/s (1 byte every 100 ms) Disk drive data rate  2,000 KB/s (1 byte every 0.5 µs) Transfer rate is too high to be controlled by software executing on the CPU

49 Conditions Required for DMA The I/O interface and memory must be connected The I/O module must be capable of reading and writing to memory Conflicts between the CPU and the I/O module must be avoided Remark: application program requests I/O service from operating system privileged instructions (i.e., only operating system software is allowed to access I/O instructions and procedures)

50 How it works? DMA controller The CPU “prepares” the DMA operation by transferring information to a DMA controller (DMAC): Location of the data on the device Location of the data in memory Size of the block to transfer Direction of the transfer Mode of transfer (burst, cycle steal) When the device is ready to transfer data, the DMAC takes control of the system buses (next few slides) Interrupt sent to CPU upon completion

51 “Taking Control” (1 of 2) CPUDMAC BR BG BGACK BR BG BGACK BR = Bus request (DMAC: May I take control of the system buses?) BG = Bus grant (CPU: Yes, here you go.) BGACK = BG acknowledge (DMAC: Thanks, I’ve got control.) Control Bus signals

52 “Taking Control” (2 of 2) DMAC issues a BG (“bus request”) signal CPU halts (perhaps in the middle of an instruction!) and issues a BG (“bus grant”) signal DMAC issues BGACK (“bus grant acknowledge”) and releases BR DMAC has control of the system buses DMAC “acts like the CPU” and generates the bus signals (e.g., address, control) for one transfer to take place Then…

53 DMA Initiation and Control

54 DMA Transfers Burst mode Burst mode This transfer is repeated until complete DMAC relinquishes control of the system buses by releasing BGACK Cycle steal mode Cycle steal mode DMAC relinquishes control of the system buses by releasing BGACK A BR-BG-BGACK sequence occurs for every transfer, until the block is completely transferred DMAC interrupts the CPU when the transfer is complete This is an example of a “completion signal” interrupt

55 BG-BR-BGACK Timing BR BG BGACK CPU cycles CPU cycles DMA cycles time

56 Burst Mode vs. Cycle Steal Mode Burst mode: Cycle steal mode: Legend: CPU cycle DMA cycle BR/BG/BGACK sequence time

57 Types of I/O DMA includes all three types of I/O. Let’s see… Programmed I/O Interrupt-driven I/O Direct memory access (DMA)

58 Program-Controlled I/O (in DMA) Data bus Address bus Control bus Memory DMAC CPU Disk The CPU “prepares” the DMAC

59 DMA Data bus Address bus Control bus Memory DMAC CPU Disk The transfer takes place

60 Interrupt-driven I/O (in DMA) Data bus Address bus Control bus Memory DMAC CPU Disk The DMAC interrupts the CPU when the transfer is complete IRQ

61 CPU-Memory-I/O Architectures: 5 Basic Components CPU I/O peripheral device Memory One or more I/O modules (act as an interface between CPU, memory, I/O devices) Buses connecting components together

62 Basic CPU-Memory-I/O Pathway

63 I/O System Architectures Bus architecture Channel architecture

64 Bus Architecture Simplest form Single system bus connects CPU to memory and modules More commonly Number of different interconnected buses Bus interfaces (expansion bus interface, bus bridges) – convert bus signals from different buses Possibility to use together Multiple vendors and industry-standard buses Open architecture

65 Bus Configuration

66 Signal Control and Implementation Multiplexing Multiplexing – address and data share the same lines (e.g. PCI bus) Burst Burst – transfer of several pieces of data in a rapid sequence once a starting address is established

67 Bus Characteristics Data width in bits carried simultaneously Throughput, i.e., data transfer rate in bits per second Topology Topology: Point-to-Point vs. Multipoint Parallel Serial Parallel (simultaneous transfer i.e., individual lines for each bit of data, address and control) vs. Serial (sequential transfer on a single data line) Use: internal (e.g., within CPU) vs. external Distance: short (parallel) Protocol

68 External Interface Buses and Ports Peripherals Peripherals - external I/O devices Port Port – a connector at the end of the bus to connect a peripheral device Port controller Port controller – general control for the port Connected to standard buses, e.g., PCI or ISA device drivers Device control is built into a controller within device and into computer software program (device drivers) Device drivers – built into operating system or supplement to it Types Types of external ports: Parallel Serial High-speed general interface bus port

69 Parallel port Originally: point-to- point bus for a single type of device No addressing required To connect printers Control lines for printer- specific signals IEEE 1284 Recent version IEEE 1284 allows sharing of multiple devices IBM PC parallel printer port Standard PC parallel signals

70 SCSI - Small Computer System Interface Parallel bus Connects CD-ROM, HD, Tape, Scanner Provides addressing for each device Designed to be “daisy chained” (each device is plugged into the previous device) Supports multiple devices from a single SCSI port

71 Serial port RS-232C Data transferred using a single data line for each direction A number of control lines Does not contain any address line A single bus to connect a single device RS-422 Faster version of RS-232C Used to connect terminals, modems, mice, network interfaces PC serial printer port (male)

72 Universal Serial Bus - USB Replaces standard serial port 480 Mega bits/sec Much faster: transfer rate – up to 480 Mega bits/sec Multipoint bus uses hierarchical connection system 127 devices Hubs provide multiple connection points for I/O devices (up to 127 devices) packets Data are transferred in packets: Device identifier Small set of data Cannot tie up the system isochronous data transfer Delivered at regular time intervals – isochronous data transfer

73 USB Root Hub Multipoint bus Hubs provide multiple connection points for I/O devices Supports 127 devices 4 lines: A single data pair (to carry data, address, control information) 2 lines - power

74 FireWire (i.link) Serial multipoint bus Designed for extremely fast data transfer – up to 3.2 Gigabits/sec FireWire devices can be “daisy-chained” or connected together with hubs Cable of two data pairs and an optional pair of power lines Each segment of the bus can handle up to 63 devices Each device controller is independent, no host bus controller is required Devices can communicate with each other without a computer Control capabilities must be built into every I/O module

75 Typical FireWire Configuration Network-like characteristics Device controllers independent

76 USB and FireWire (IEEE 1394) Both serial, multipoint bus specifications Add/remove devices w/o powering down Packet protocol for isochronous data transfer Isochronous: delivery at regular time intervals Guarantee specified throughput

77 USB vs. FireWire USB: slow to medium speed data transfer applications, i.e., storage devices 12 Mbits/sec USB-2: high-speed data transfer 480Mbits/sec FireWire: high-speed data transfer, i.e., full motion video with sound 400 Mbits/sec to 3.2 Gbits/sec

78 I/O System Architectures Bus architecture Channel architecture

79 Channel Architecture Used in all IBM mainframe computers since late 70s channel subsystem Based on channel subsystem Separate I/O processor that serves as a separate computer for I/O operations channel control words Own set of instructions (channel control words) Programs stored in memory, independent of CPU Transfer data between memory and an I/O device using DMA Subchannels Connected to a control unit module through one or more channel paths Similar role to a device controller Up to 8 different channel paths between channel subsystem and control unit (used as alternative, if busy)

80 I/O Channel Architecture

81 More Computer humour More Computer humour