Ultra high speed heterojunction bipolar transistor technology Mark Rodwell University of California, Santa Barbara , fax 2001 GOMAC Conference

Scaling and high speed electronics Fast electronics: 10, 40,160 …(?) Gb/s fiber optics Gigabit radio on 60 GHz band 180 GHz amplifiers, sensitive 2.5 THz diode mixers cheap 2 GHz phones, cheap 1 GHz PCs, cheap 20 GHz TV electronics gets ~10:1 faster each decade Are we reaching the limits ?...radically different materials ?...resonant tunneling ?? …the electronic bottleneck ? Improving high frequency devices by Scaling: dimensions, current density, contacts near-THz transistors, ~10 THz diodes, towards 100-GHz logic  applications in ADCs/DACs for RADAR Fast electronics can still get much faster

Bandwidth of bipolar transistors: current-gain cutoff frequency Thinner base, thinner collector  higher f , but….

Bandwidth of bipolar transistors: power-gain cutoff frequency Thinner base, thinner collector  more base resistance, more collector capacitance  reduced power gain cutoff frequency f max What matters: f t or f max ? How do we scale device to get high values for both ?

for x 2 improvement of all parasitics: f t, f max, logic speed… base  2: 1 thinner collector 2:1 thinner emitter, collector junctions 4:1 narrower current density 4:1 higher emitter Ohmic 4:1 less resistive Scaling Laws for fast HBTs Challenges with Scaling: Collector mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length sets minimum size for collector Emitter Ohmic: hard to improve…how ? Current Density: dissipation, reliability Loss of breakdown avalanche Vbr never less than collector Egap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power Narrow-mesa with 1E20 carbon-doped base undercut-collector transferred-substrate

Tuned ICs (MIMICs, RF): fmax sets gain, & max frequency, not ft. …low ft/fmax ratio makes tuning design hard (high Q) Lumped analog circuits need high & comparable ft and fmax. (1.5:1 fmax/ft ratio often cited as good…) Distributed Amplifiers in principle, fmax-limited, ft not relevant…. (low ft makes design hard) What HBT parameters determine analog bandwidth ?

f max does not predict digital speed f  does not predict digital speed C cb  V logic /I c is very important  increased III-V current density is critical C cb R ex is very important R bb (C je +g m  b +g m  c ) is important 120 GHz clock predicted What HBT parameters determine logic speed ? MS latch: key digital element : resynchronizes data to clock often sets system maximum clock

What is needed for 200 GHz Logic ? UCSB Miguel Urteaga SPICE simulation Interconnects are not considered.

Transferred Substrate HBTs UCSB “transferred substrate” process allows lateral scaling of collector. Record f max more than tripled. Most circuits demand high f t. Laterally scalable device allows f max to be retained when f t is improved by vertical scaling. finite-element device simulation

Submicron Transferred-Substrate HBT UCSB Michelle Lee 3000 Å collector 400 Å base with 52 meV grading AlInAs / GaInAs / GaInAs HBT (?)

Submicron HBT Program UCSB Miguel Urteaga High Fmax Transistor Measurement ( K< 1 at all measured frequencies) GHz Unilateral power gain: high but difficult to measure fmax appears to be near 1 THz. Future work must address: improved 220 GHz measurements, measurements at > 220 GHz. Unpublished MSG U

Record f  HBT UCSB Yoram Betser Emitter 1 x 8  m 2, Collector 2 x 8.5  m Å collector 300 Å base with 52 meV grading AlInAs / GaInAs / GaInAs HBT

Record f  HBT UCSB Yoram Betser 290fs 105fs 82fs20fs39fs537fs

Fast InP DHBTs for higher power f   = 165 GHz; f max = 303 GHz 5 V breakdown at 10 5 A/cm 2 >9 V at 2*10 4 A/cm 2 UCSB pk Sundararajan M Dahlstrom 1x 8 micron emitter, 2x 10 micron collector 3 kÅ collector, 400 Å base f   = 216 GHz; f max = 210 GHz 4 V breakdown at 10 5 A/cm 2 >6 V at 2*10 4 A/cm 2 2 kÅ collector, 400 Å base 6.2 DHBT program 1x 8 micron emitter, 2x 10 micron collector

200 GHz Single-Stage Amplifier Single-stage Reactively-tuned amplifier at 180 GHz with 6 dB gain Gain-per-stage ~2:1 higher than HEMT amplifiers at same frequency Simple design to provide directions for future work Future Work: Multi-stage amplifiers with improved devices Measured Gain Submicron HBT Program Measured Return Loss UCSB Miguel Urteaga

InP-HBT W-band Amplifiers balanced amplifier: 10.7dBm at 78GHz (transferred-substrate HBT) InGaAs-collector:  V br =1.5 V  low power InP-collector:  V br ~5 V  higher powers expected UCSB ARO common-base amplifier: 9.7dBm at 82.5 GHz James Guthrie

High Speed Amplifiers 18 dB, DC--50+ GHz UCSB Dino Mensa PK Sundararajan 8.2 dB, DC-80 GHz >397 GHz gain x bandwidth from 2 HBTs S 22 S 11 S 21

HBT distributed amplifier UCSB PK Sundararajan 11 dB, DC-87 GHz AFOSR TWA with internal ft-doubler cells

75 GHz HBT master-slave latch connected as Static frequency divider re-fabricated 1999 (Q. Lee) UCSB design In 1999 operated to 66 GHz limit of available sources technology: 400 Å base, 2000 Å collector HBT 0.7 um mask (0.6 um junction) x 12 um emitters 1.5 um mask (1.4 um junction) x 14 um collectors 1.8  10 5 A/cm 2 operation, 180 GHz ft, 260 GHz fmax simulations: 95 GHz clock rate in SPICE test data to date: tested, works over full and GHz bands now testing in GHz band (limited signal power) UCSB Thomas Mathew Hwe-Jong Kim modulation is synthesizer 6 GHz subharmonic 3.92 V, 224 mA, 0.88 W 200 GHz Logic Program ~3.5 dBm input power

19 GHz adder-accumulator Objectives: GHz clock rate adder for 20 GHz DDS Approach: building blocks for a pipelined adder Simulations: GHz clock rate in SPICE Significance: Design to meet 20GHz DDS requirements Status: Component blocks built, working at 19 GHz UCSB Thomas Mathew

20 GHz  ADC Design comparator is 75 GHz flip flop DC bias provided through 1 K  resistors Integration obtained with 3 pF capacitors RTZ gated DAC Integrated Circuit 150 HBTs, 1.2 x 1.5 mm, 1.5 W UCSB ONR ADC Program S Jaganathan

Submicron device scaling: towards THz bandwidths Scaling drift-diffusion electron devices for 2 x increased speed: 2 x thinner layers, 4 x narrower junctions 4 x higher current density, 4 x improved vertical contacts Results with submicron III-V HBT scaling: 300 GHz f , high (1100 GHz ?) f max Challenges with scaling: power density, improved vertical contacts, breakdown Opportunities: aggressive parasitic reduction of III-V's (as in Silicon) III-V HBT scaling to below 0.1 um Prognosis: much faster transistors, amplifiers, and logic are still feasible

In Case of Questions

Submicron Transferred-Substrate HBT UCSB Michelle Lee

Why Mason’s Gain, U, is used to find f max : MAG/MSG can be above U MAG/MSG can be below U U is same for CE, CB, & CC U is not changed by pad parasitics U has -20 dB / decade slope to f max MSG slope is -10 dB / decade MAG has no fixed slope -for hybrid-  model comment: U is not given by: (CE, small C cbx ) ( CE, large C cbx )...above -20 dB/dec line …below -20 dB/dec line Plots generated using HP / EESOF simulator and standard hybrid-  model

DC-50 GHz & GHz Network Analysis  waveguide-coupled micro-coax probes Parasitic probe-probe coupling S 12 error background: not corrected by calibration  gain measurements corrupted, worse for W-band Measuring High f max Transistors I corrupted W-band measurement

Offset reference planes, on-wafer LRL calibration standards separate probes to reduce coupling reference planes at transistor terminals Measuring High f max Transistors II 230  m

Line-reflect-line on-wafer cal. standards LoLo LoLo LoLo LoLo LoLo LoLo L o +L o L o +560  m+L o L o  m+L o GHz LINE GHz LINE THROUGH LINE SHORT OPEN (reflect) DUT GHz Calibration standards GHz Calibration standards Calibration verification Device under test V= 2.04 x 10 8 m/s (  r = 2.7)

185 GHz Single-Stage Amplifier: High f max demonstration Single-stage reactively-tuned amplifier at 185 GHz with 3.0 dB gain Gain-per-stage is comparable to results from HEMT technologies Simple design to provide directions for future work Future Work: Multi-stage amplifiers with improved devices Measured Gain 6.2 Submicron HBT Program also supported by AFOSR

Ultra-High f max Transferred-Substrate HBTs Transferred-substrate process results in dramatic reduction in collector base capacitance (Ccb) Sub-micron scaling of emitter and collector widths has resulted in record values for extrapolated f max (1 THz) Improved E-beam lithography at UCSB will allow more aggressive device scaling Reduce base resistance with carbon base doping and improved base Ohmics Goal: Build the World’s Fastest Electron Device 6.2 Submicron HBT Program Sub-micron HBT measured from 0-50 GHz and GHz High speed device measurements require careful attention to measurement and calibration methodology