An Efficient Implementation of Scalable Architecture for Discrete Wavelet Transform On FPGA Michael GUARISCO, Xun ZHANG, Hassan RABAH and Serge WEBER Nancy University - Laboratoire d’Instrumentation Electronique de Nancy (LIEN) {michael.guarisco, xun.zhang, hassan.rabah, Purpose and Goals Purpose and Goals: The aim of this study is to implement a new efficient architecture of DWT on FPGA (Field Programmable Gate Array). This architecture has to be scalable, i.e. it has to adapt to any size of picture, achieve many levels of computing and especially respect some real time processes. System Architecture System Architecture: Detailed operations: Conclusion and future work: The scalability of this architecture is achieved by the memory blocks which can adapt to the picture size. The number of levels which can be performed is theoretically infinite, by dint of this, the design can transform a picture in a predefined time independently of the number of levels. Furthermore, our architecture accept many type of filter to adapt itself at different picture types. Discrete Wavelet Transform: DWT is computed by successive low-pass and high-pass filtering. The low pass result is then filtered by the same process and this computing is repeated until each level has been performed. At the end of each level of transform the result is decimated horizontally and vertically so as to obtain four groups of data representing each a picture four times smaller than the original picture. The iterative nature of the transform generates the necessity of storing intermediate results. In our architecture the DWT is designed to exploit efficiently the inherent processing parallelism. Data organization in internal memory. This organization allows the processing unit to have parallel access in the memory. On this figure, each pixel of the original picture is labeled by a letter (S or D) and a number in the order of their appearance at the input of the Data in Organization Unit. This unit is then charged to reorganize pixel data in a special way to ensure that two consecutive pixels can be read at the same clock edge. The process units compute first the 1D-DWT in line, then in columns. Two consecutive lines (or two consecutive rows) are computed independently in parallel thanks to the two process units. Let be T load the necessary time to fill one memory block with data of one picture. T load is only dependant of the frequency work and the picture size. Using two PE, the execution time is always inferior to the loading time, no matter what number of levels we have to perform. We demonstrate that this execution time is equal to the following numeric suite, where n is the number of levels : Three controllers and three memory blocks, each may contain a whole picture or a macro block picture, are needed. The control unit has to deal with the multiple data paths and switch each controller with the right memory at the right time. This diagram presents the execution time of different levels of DWT in respect to the loading time Processing elements (PE1 & 2) are hinging on the filter type only. Control Unit is described as a finite state machine and depends on the desired number of level and picture size. Its role is to generate the addresses which are needed to read and write the memory. Each of the three memories is cut in four parts to allow parallel treatment. The internal structure of the executing process unit :