doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide requirements of QoS Steven D. Williams / Intel Benno Ritter / Philips

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 2 Goals of this presentation Make case for meeting the needs of 1394 in the TGe QoS specification Limited 1394 primer – enough for 1394 QoS Miscellaneous issues What 1394 requires of wrt QoS

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 3 Background 1394 is the overwhelming CE connectivity choice – Mbps, isochronous, TCP/IP –Wide adoption in Europe-Japan, N.America. by 2002 CE community believes that 1394 will be the choice for home network wired backbone –The issue is bandwidth Big drawback: requires new wires Big opportunity: Until new wires, wireless!

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 4 Environment Hiperlan/2 includes a 1394 convergence layer as part of HL/2 specification suite 1394 Trade Association Wireless Working Group –Working on an Protocol Adaptation Layer Contingent on QoS meeting QoS needs –There are calls to create a common approach to bridging across any wireless medium Hiperlan/2, MMAC

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 5 Goals of 1394 Low cost, high performance interconnect plug ‘n play Compatible architecture with other IEEE busses –Follow IEEE 1212 CSR (Control and Status Register) standard Peer-to-peer read/write memory model for asynchronous services –NOT an I/O channel Isochronous service –Deliver high definition video and high-quality audio

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 6 Definition: Isochronous Signals which are dependant on some uniform timing or carry their own timing information embedded as part of the signal. 1 –Cell phone systems, particularly G2, may be isochronous because the handset A/D that collects sound samples is phase-locked to the cell controller. –TV is isochronous because the H and V oscillators in the receiver are phase locked to the H and V sync pulses in the transmitted signal 1 - The ATM Dictionary,

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 7 Definition: Plesiochronous Signals which are arbitrarily close in frequency to some defined precision. They are not sourced from the same clock and so, over the long term, will be skewed from each other. Their relative closeness of frequency allows a switch to cross connect, switch, or in some way process them. That same inaccuracy of timing will force a switch, over time, to repeat or delete frames (called frame slips) in order to handle buffer underflow or overflow. 3 –Current phone systems are plesiochronous –Internet media delivery is plesiochronous 1 - The ATM Dictionary,

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide Topology Acyclic tree Any node may be root Location is arbitrary Communication is peer- to-peer Certain nodes perform bus mgmt. duties Audio System DVD ScannerCPU Hard Disk Video Display Printer Digital Camera Bridge

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide Isoch characteristics Assumed: –Late data is useless – never retry, never ACK Bounded Jitter – guaranteed timing –Buffer requirements are small A node keeps its bandwidth allocation until: –It explicitly shuts down its channel, or –It leaves the network unannounced –bus reset returns allocated bandwidth Bit error rate is small –

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide Isochrony Supported by 125 μSecond bus cycles Management by bus ‘officers’ –Cycle master – issues Cycle Start packets –Isoc Resource Manager (IRM) Allocates bandwidth as time allocations during cycles Allocates channels – there are 63 channels If no isoc nodes, no cycles or isoc bus officers are needed or are present

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide Cycles Cycles are 125 μSeconds long on average –Up to 80% of cycle may be allocated to isoc talkers –Cycle master sends cycle start packets seen by all nodes –Cycle starts may be temporarily pre-empted by an async packet in progress, but clock is not shifted Same as TBTT model –Cycles consist of first an isochronous period and then an asynchronous period Cycle Start Cycle Start 125 μS Chan i Chan n Isoc (short) gaps Async Packet Async Packet b Async (long) gaps Nominal Cycle Start time This cycle start was delayed by Preceding async Packet & ACK End of isoc period indicated to async talkers by no traffic at end of isoc gap Channels j, …, n-1 Not to scale, cycle start packets are very short, low overhead ACKACK ACKACK …

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 12 Bus Reset and Bus Officers Bus reconfiguration occurs after every bus reset –When any node leaves/enters the bus and other specific events –Bias for re-election of incumbents –Bus is re-enumerated on reset –Isochronous streams undisturbed by bus resets –Reconfiguration typically completes within 10 μSec Officers are: –Root – Decides who wins arbitration in 1394 –Cycle Master – governs isoc bus timing – if present, is root –Isochronous Resource Manager (IRM) – allocates channels & bandwidth –Bus Manager – Keeps topology, power dist. mngr., etc.

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide Bridging 1394 buses may be connected by bridges –Up to 1024 buses in a bridged network Timing is propagated across bridges to support isoc delivery Nodes of a bus that connect with other buses are called portals –Each bus may have multiple bridge portals, but one alpha portal which dictates timing from bridge

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide Bridging Diagram Each portal is a node on a bridged bus Bridges pass isoc & async traffic Clock passed across the bridge An bridge supports these functions Portal Control Portal Control Request FIFO Isochronous FIFO Request FIFO Response FIFO Isochronous FIFO Tran Phy Link Cycle Clock Routing Tables Configuration ROM Tran Phy Link

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 15 Additional considerations Home 1394/ may be ad hoc –Trials at Microsoft –Requires that a point coordinator be elected for QoS from amongst ad hoc STAs More broadly, will QoS be available in ad hoc networks? How would it work? Bandwidth allocation in QoS scheme must be accessible by the 1394 bridge One HDTV channel is 24 Mbps including audio, FEC would increase this

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide 16 References 1394 Trade Association:

doc.: IEEE /164 Submission Steven D. Williams / Intel et al March 2001 Slide Specification Family IEEE , 1394a-2000, 1394b-200x High Speed Serial Bus –“Memory-bus-like” logical architecture, isochronous support –Serial implementation of 1212 architecture IEEE , x CSR Architecture –Standardized addressing, well-defined control and status registers, standardized transactions “Higher layer” protocols –NCITS SBP-2 integrates DMA into I/O process RBC (for mass storage) and IEEE P PPDT (for printers) –IEC and 1394TA AV/C standards define control and data for A/V devices –RFC 2734 defines Internet Protocol over 1394 –Digital Transport for Content Protection (“5C”/DTLA) More under development –p for bridges, IIC for instrumentation and industrial control, DPP for consumer cameras/printers, etc.