Huang-Yu Chen †, Mei-Fang Chiang †, Yao-Wen Chang † Lumdo Chen ‡, and Brian Han ‡ Novel Full-Chip Gridless Routing Considering Double-Via Insertion † The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taiwan ‡ UMC, Taiwan

2 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Experimental Result  Conclusion

3 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Experimental Result  Conclusion

4 Redundant-Via Insertion  Via-open defects  Via-open defects are one of the dominant failures due to the low-k, copper metal process in the nanometer era  Redundant-via insertion  Redundant-via insertion is highly recommended by foundries to improve via yield and reliability  Double vias have 10X 100X smaller failure rates than single vias 90nm copper interconnect (source: TSMC) double-via insertion metal 1 metal 2 via redundant via

5 Dead, Alive, and Critical Vias redundant-via candidate  For a via, a redundant-via candidate is its adjacent position where a redundant via can be inserted  Via categories:  Dead via:  Dead via: the via with no redundant-via candidate  Alive via:  Alive via: the via with at least one redundant-via candidate  Critical via:  Critical via: the via with exactly one redundant-via candidate critical via dead viaalive vias metal 1 metal 2 via redundant-via candidate

6 S T S T Redundant-Via Aware Routing  Traditionally, double-via insertion is focused on the post-layout stage  Minimizing dead and critical vias during routing  Minimizing dead and critical vias during routing can increase the post-layout double-via insertion rate by 15 25%  Dead vias cannot be paired with redundant vias  Critical vias may not be paired due to competition with others S T a bad path a better path dead via alive via a routing instance

7 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Experimental Result  Conclusion

8 Multilevel Routing  Billions of transistors may be fabricated in a single chip  Multilevel routing  Multilevel routing has demonstrated the superior capability of handling large-scale designs Already-routed net To-be-routed net coarseninguncoarsening ‧ global routing ‧ detailed routing ‧ failed nets rerouting ‧ refinement

9 Observations global and detailed routing are intertwined with each other  In the coarsening stage, global and detailed routing are intertwined with each other at each level  Advantage:  Routing resource estimation is accurate Information of previously routed nets is exactly known  Disadvantage:  Optimization freedom is limited Refinement takes a lot of efforts and the solution easily falls into local optima Need more flexibility to address nanometer electrical effects

10  Separate  Separate global routing and detailed routing  Effectively perform global and detailed routing optimization  Pre-analyzecongestion  Pre-analyze congestion to assist resource estimation bottom-up  Apply bottom-up routing approaches to handle local circuit effects  Better for routability, congestion, and via minimization  Redundant-via planning is a local effect Maximize the optimization freedom Ideas for Improvements

11 Our Two-Pass, Bottom-Up Routing Framework To-be-routed net Already-routed net G0G0 G1G1 G2G2 coarsening First Pass Stage Second Pass Stage Prerouting Stage high low coarsening G0G0 G1G1 G2G2 global routing Apply global routing for local nets and iteratively refine the solution detailed routing Use detailed routing for local nets, reroute failed nets, and estimate resources level by level congestion hot spots Identify congestion hot spots based on the routing topology of each net

12 Redundant-Via Aware Routing Congestion-Prediction Prerouting Via-Minimization Global Routing Redundant-Via Aware Detailed Routing

13 congestion-prediction prerouting Congestion-Prediction Prerouting  Predict congestion hot spots to guide the following routing for better congestion minimization  Help to reduce detours and thus the via count  Alleviate post-layout double-via insertion efforts global tile congestion-minimization global routing routing topology

14 S T Probabilistic Congestion Model  Predict congestions based on the probabilistic distribution of 1- and 2-bend global routes probabilistic congestions S T +3/5 +1/5 +2/5 +1/5 +2/5 +1/5 +3/5 +1/5 +2/5 +1/5 +2/5 +1/5 five 1- and 2-bend global routes may become congestion hot spot

15 Via-Minimization Global Routing pattern routing  Apply congestion-driven global pattern routing [TCAD’02] to reduce via counts  Uses L-shaped (1-bend) and Z-shaped (2-bend) connections to route nets  Has lower time complexity than maze routing L-shaped (1-bend) connectionZ-shaped (2-bend) connection

16  The objective is to minimize dead and critical vias  Router should select a path that passes through the fewest redundant-via candidates in the routing graph  It may incur more detours and thus more vias  Must consider (1) redundant-via planning and (2) via minimization simultaneously via countredundant-via related penalty  Take the via count and redundant-via related penalty as the cost to guide the detailed maze routing Redundant-Via Aware Detailed Routing Cost function for a net n: V n : #via, P n : redundant-via related penalty.

17 Redundant-Via Related Penalty  Degree of Freedom of via v (DoF v ):  # of redundant-via candidates of v  Set the cost of redundant-via candidate r as S T 1/3 1/4 1/2 metal 1metal 2via redundant-via candidate S T penalty = 5/6 penalty = 1/4 ? ? { max{ } | v i is the via that shares r }

18 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Experimental Result  Conclusion

19 Post-Layout Double-Via Insertion Problem  Given a post-routing layout, pair each via with one redundant via as many as possible without incurring any design-rule violation  Different approaches may affect the insertion result 2 vias are paired 3 vias are paired metal 1 metal 2 via redundant via Better Yield

20 Previous Work  Yao et al. [GLSVLSI’05] mentioned that post-layout double-via insertion can be solved by maximum bipartite matching maximum bipartite matching formulation is incorrect for some cases  Lee and Wang [ASPDAC’06] showed that maximum bipartite matching formulation is incorrect for some cases maximum independent set (MIS)  Lee and Wang used maximum independent set (MIS) to solve the problem and applied heuristics to speed up MIS is NP-complete, high time complexity

21 A Troublesome Example v2v2 v3v3 v1v1 v1v1 v2v2 v3v3 V 2 and V 3 cannot be paired simultaneously (horizontal design-rule conflict) v2v2 v3v3 v1v1 v1v1 r2r2 v2v2 v3v3 v2v2 v3v3 v1v1 v1v1 r1r1 v2v2 v3v3 V 1 and V 3 cannot be paired simultaneously (vertical design-rule conflict) routing layout cross-section view metal 1 metal 2 via12 redundant-via candidate metal 3 via13

22 Bipartite Graph Formulation Problem V 2 and V 3 cannot be paired simultaneously v1v1 r2r2 v2v2 v3v3 v1v1 r1r1 v2v2 v3v3 V 1 and V 3 cannot be paired simultaneously v1v1 r1r1 r2r2 v2v2 v3v3 a bipartite formulation v2v2 v3v3 v1v1 v2v2 v3v3 v1v1 v2v2 v3v3 v1v1 v1v1 r 1,2 v2v2 v3v3 another bipartite formulation v1v1 r1r1 v2v2 v3v3 v1v1 r2r2 v2v2 v3v3 Infeasible Lack optimality best result ?

23 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Optimal Algorithm for up to 3 Routing Layers  On-Track/Stack Redundant-Via Enhancement  Two-Stage Double-Via Insertion (TDVI) Algorithm  Experimental Result  Conclusion

24 Our Bipartite Formulation stack via is treated as one unit via up to 3 layers maximum bipartite matching  If stack via is treated as one unit via, the double-via insertion for designs with up to 3 layers can be optimally solved by maximum bipartite matching  A polynomial-time optimal algorithm for the restricted case  The troublesome example can be accurately formulated v1v1 v2v2 routing layout redundant-via candidate metal 1 metal 2 via12 metal 3 via13 r2r2 v2v2 v3v3 r v1v1 v2v2 v1v1 v2v2 cross-section view v2v2 v1v1 r2r2 v2v2 v3v3 r v1v1 v2v2 v2v2 v1v1 v 2 is pairedv 1 is paired

25 r 4,5 v1v1 v2v2 r1r1 r2r2 r3r3 r6r6 Alive Vias Redundant-Via Candidates v3v3 r9r9 r 7,8 final bipartite graph Optimal Algorithm for up to 3 Layers metal 3 metal 1metal 2via23 redundant-via candidate via12 v1v1 v2v2 r1r1 r2r2 r3r3 r4r4 r5r5 r6r6 Alive Vias Redundant-Via Candidates v3v3 r7r7 r8r8 r9r9 v1v1 v2v2 r1r1 r6r6 v3v3 r8r8 r2r2 r3r3 r4r4 r7r7 r9r9 r5r5 r8r8 v2v2 r7r7 v3v3 design-rule conflict between r 7 and r 8 routing layout initial bipartite graph

26 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Optimal Algorithm for up to 3 Routing Layers  On-Track/Stack Redundant-Via Enhancement  Two-Stage Double-Via Insertion (TDVI) Algorithm  Experimental Result  Conclusion

27 Preference for On-Track/Stack Redundant Via  Redundant vias can be placed on-track or off-track.  If a redundant via is placed on the wire segment of its corresponding via, it is on-track; otherwise, it is off-track on-track stack  Prefer on-track and stack redundant vias for double- via insertion  On-track redundant vias consume fewer routing resources  Better to protect stack vias which have lower yield than single vias r1r1 r2r2 r3r3 r4r4 r6r6 r5r5 v1v1 v2v2 on-track metal 1 metal 2 via12 redundant-via candidate metal 3 via23 routing layout off-track

28 On-Track/Stack Redundant-Via Enhancement weighted bipartite graph minimum weighted bipartite matching  Construct the weighted bipartite graph and use minimum weighted bipartite matching to solve  For via v and its redundant-via candidate r, define weight w(v, r) as follows: stack redundant via preference on-track redundant via preference w(v,r) = tr/N, if v is a stack via containing N single vias; tr, if v is a single via. tr = 1, if r is on-track; 2, if r is off-track.

29 Double-Via Insertion with Preference routing layout r1r1 r2r2 r3r3 r 4,5 r6r6 r 7,8 r9r / v1v1 v2v2 v3v3 weighted bipartite graph redundant via r4r4 v1v1 v2v2 r1r1 r2r2 r3r3 r6r6 r7r7 v3v3 r9r9 r8r8 r5r5 metal 3metal 1 metal 2 redundant-via candidate via23 via12via24 metal 4 insertion result with preference v1v1 v2v2 v3v3 r1r1 r6r6 r9r9

30 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Optimal Algorithm for up to 3 Routing Layers  On-Track/Stack Redundant-Via Enhancement  Two-Stage Double-Via Insertion (TDVI) Algorithm  Experimental Result  Conclusion

31 LbLb LbLb LtLt LtLt Two-Stage Double-Via Insertion Algorithm 1. Partition the layout into sublayouts with at most 3 layers, s.t. # of design-rule conflicts between sublayouts is minimized v1v1 v2v2 v3v3 v4v4 r3r3 r7r7 v6v6 r4r4 r8r8 metal 1metal 2 metal 3metal 4 via redundant-via candidate r1r1 r2r2 r6r6 r5r5 v5v5 conflict

32 criticality = 2 criticality = 0 Two-Stage Double-Via Insertion Algorithm criticality 2. Decide the priority of each sublayout by criticality  For redundant-via candidate r that has design-rule conflicts with the different sublayout, criticality c r = # of induced dead vias after inserting r; otherwise, c r = 0  Criticality of sublayout L = Σ c r, where r is inside L v1v1 r1r1 r4r4 v5v5 v2v2 v3v3 v4v4 r7r7 r5r5 v6v6 r8r8 metal 1metal 2 metal 3metal 4 via redundant-via candidate Criticality: 0 r2r2 r3r3 r6r6 conflict Criticality: 2 LbLb LbLb LtLt LtLt

33 Two-Stage Double-Via Insertion Algorithm 3. Solve sublayouts in the non-decreasing order of criticality  If one sublayout is solved, update its adjacent sublayouts by removing the infeasible redundant-via candidates v1v1 r1r1 r4r4 v3v3 r3r3 r6r6 r5r5 metal 1metal 2 metal 3metal 4 via redundant-via candidate Criticality: 0 Criticality: 2 LbLb LbLb r1r1 r2r2 v1v1 v2v2 v3v3 v4v4 v5v5 v6v6 r 7,8 r 4,5 r3r3 v5v5 conflict LtLt LtLt v2v2 v4v4 r7r7 v6v6 r8r8 r2r2

34 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Experimental Result  Conclusion

35 Experimental Setting  Platforms  Routing system: 1.2 GHz Sun Blade 2000  Double-via insertion algorithm: 3.2 GHz Intel Pentium 4  DRC verification: Cadence SoC Encounter  MCNC benchmark: CircuitSize (um 2 )#Layer#Net#Pin Mcc × Mcc × Struct4903 × Primary × Primary × S × S × S × S × S × S ×

36 Gridless Routing Comparison  Compared with the gridless router  Reduce the via count 20% over MGR [ASPDAC’05]  Reduce the via count 24% over VMGR [ASPDAC’06]

37 Redundant-Via Aware Detailed Routing  Consider redundant vias during detailed routing  1.4X fewer dead vias and 1.1X fewer critical vias  2% slight increase in the via count

38 Post-Layout Double-Via Insertion  Compared with H3K [ASPDAC’06]  71X runtime speedup  A higher insertion rate (98.6%) and a higher on-track rate (79.2%)

39 Double-Via Insertion of S5378

40 Local View of Insertion Results

41 Outline  Introduction  Redundant-Via Aware Two-Pass Routing System  Post-Layout Double-Via Insertion Algorithm  Experimental Result  Conclusion

42 Conclusion  We have developed a redundant-via aware gridless routing system  Reduced via counts  Obtained fewer dead vias and critical vias  We have proposed a post-layout double-via insertion algorithm  Resulted in a higher insertion rate  Resulted in a higher on-track rate  Achieved at least one-order runtime speedup

43 Thank You!

44 Q & A