Implementation of a Simple 8-bit Microprocessor with Reversible Energy Recovery Logic Seokkee Kim and Soo-Ik Chae System Design Group School of Electrical Engineering Seoul National University 2005 / 05 / 05

SDGroup, School of Electrical Engineering, SNU 1/15 Contents Introduction to nRERL 8-bit nRERL Microprocessor Phase Scheduling Reversibility Breaking Measurement Results Future Works

SDGroup, School of Electrical Engineering, SNU 2/15 nRERL is nMOS Reversible Energy Recovery Logic *) –A Fully adiabatic circuit using reversible logic –Only nMOS SW is used by exploiting Bootstrapped –Phase-pipelining using 6-phase clocked power Introduction to nRERL (1) *) J. Lim, D.-G. Kim, and S.-I Chae, “nMOS reversible energy recovery logic for ultra-low-energy applications,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp , June, F -1 F  i+4 G -1  i+3  i+2  i+1 G  i+5 H -1  i+4  i+3  i+2 H  i+3  i+2  i+1 ii XiXi X i+1

SDGroup, School of Electrical Engineering, SNU 3/15 Introduction to nRERL (2)  i+1 ii  i+2  i+3 XiXi M FL M FLB M FI M FIB M RL M RLB M RI M RIB n1n1 XiXi X i+1 n2n2 n3n3 n4n4 clamp Reverse Logic switch Reverse Isolation switch Forward Logic switch Forward Isolation switch

SDGroup, School of Electrical Engineering, SNU 4/15 8-bit nRERL Microprocessor (1) Issues –Area v.s Reversibility :How we should control the reversibility to integrate the microprocessor in the limited silicon area ? –Pipelining v.s Energy :How we should schedule the phase pipelining to minimize the total energy consumption of the microprocessor ? –Energy v.s Reversibility :How we could control the reversibility without increasing the total energy consumption of the microprocessor ?

SDGroup, School of Electrical Engineering, SNU 5/15 8-bit nRERL Microprocessor (2) A subset of DLX Instruction Set Architecture –No floating point Instructions –19 Instructions 5 macro-blocks: –IF  ID  EXE  MEM  WB –Fully adiabatic circuit 6-phase CPG is also integrated –A shared off-chip inductor is used Register File (16w x 8b) Register File (16w x 8b) ALU RAM (128w x 8b) RAM (128w x 8b) Controller 6-phase Clocked Power Generator clocked power data flow path 8-bit adiabatic Microprocessor Off-chip f OSC f REF Program Counter(PC) Program Counter(PC) Branch PC Generator Branch PC Generator ROM (64w x 20b) ROM (64w x 20b)

SDGroup, School of Electrical Engineering, SNU 6/15 Phase scheduling (1) Register File Register File Memory ALU Register File Register File Memory ALU Buffer T0T0 T1T1 T2T2 T3T3 T4T4 T5T5 T6T6 T7T7 T8T8 T9T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T Phase Time Register File Register File Memory ALU Writeback data CASE I: Cycle-based  scheduling CASE II: Phase-based  Scheduling (best case) CASE III: Phase-based  Scheduling (worst case)

SDGroup, School of Electrical Engineering, SNU 7/15 Phase scheduling (2)

SDGroup, School of Electrical Engineering, SNU 8/15 Reversibility Breaking (1) SERC: Self-Energy Recovery Circuit –Energy recovery with its own data instead of using reversible logic –Nonadiabatic loss exists ( ) T2T2 T3T3 T4T4 T5T5 T6T6 T7T7 0 44 Data* 55 0 0 V thb 0 n7 V thb T8T8 Data* n7 n8 44 55 Data* 44 00 11 11 22 22 33 SERC Data

SDGroup, School of Electrical Engineering, SNU 9/15 Reversibility Breaking (2) Infinite memory cannot be implemented on the limited silicon area SERC is used for unwrite and refresh operations.

SDGroup, School of Electrical Engineering, SNU 10/15 Measurement Results Bias generator Bias CPG Memory ALU & Register file ROM & PC Control 6-phase Clocked Power Routing microprocessor core ANAM 0.18  m (1P6M) –Core: 2.62 x 2.03 mm 2 –CPG: 1.0 x 0.6 mm 2 –V dd =1.8V, V th0 =0.35V –E=8.5 pJ/cycle (P=7.5  V dd =1.8V, f=880kHz E_cpg = 4.97 pJ/cycle (58.5%) E_core = 3.53 pJ/cycle (41.5%)

SDGroup, School of Electrical Engineering, SNU 11/15 Hardware Complexity # of transistors (Portions to Core) Area (Portions to Core) ROM (64w x 20b)10,000 (13.3%)0.60 x 0.50 mm 2 (7.9%) PC17,000 (22.6%)0.60 x 0.58 mm 2 (9.2%) ALU5,200 (6.9%)0.50 x 0.60 mm 2 (7.9%) Reg.file (16w x 8b)7,600 (10.1%)0.36 x 0.50 mm 2 (4.8%) Forward400 (0.5%)0.70 x 0.24 mm 2 (4.4%) RAM (128w x 8b)28,000 (37.2%)0.65 x 1.30 mm 2 (22.3%) Control5,700 (7.6%)1.60 x 0.70 mm 2 (22.2%) Phase aligning buffers1,400 (1.9%)- Microprocessor core75,300 (100%)2.62 x 2.03 mm 2 (100%) CPG2, x 0.60 mm 2 Clock routing-0.4 x 7.0 mm 2 Total chip78, x 4.0 mm 2

SDGroup, School of Electrical Engineering, SNU 12/15 Energy Partitions The energy portion of CPG is more than a half. –More optimization is required for CPG design. At optimal condition, Adiabatic, Leakage, CPG rail- driver energy loss should be same.

SDGroup, School of Electrical Engineering, SNU 13/15 Comparisons (1): CMOS v.s nRERL Minimum Energy Consumption

SDGroup, School of Electrical Engineering, SNU 14/15 Summary 8-bit nRERL microprocessor 8-bit CMOS microprocessor Hardware Complexity # of Tr’s78,00015,000 Core Area2.62 x 2.03 mm x 0.51 mm 2 Operating Region Supply voltage 1.8V0.8V ~ 1.8V Frequency200kHz ~ 10MHz~ 1GHz Minimum energy consumption (optimal condition) 8.5 V dd =1.8V, V bias =1.5V, f=880kHz 52.0 V dd =0.65V, f=200kHz ~1MHz

SDGroup, School of Electrical Engineering, SNU 15/15 Future Works More energy-efficient CPG design is required. More study on the complexity reduction is required for the implementation of more complex circuits. *) *) Seokkee Kim and S.-I Chae, “Complexity reduction in an adiabatic microprocessor using reversible logic,” will be published on proc. International Symposium on Low Power Electronics and Design, Aug., 2005.