Design & Co-design of Embedded Systems Next Step: Transaction-Level Modeling Maziar Goudarzi.

Slides:



Advertisements
Similar presentations
Synthesis of Protocol Converter Using Timed Petri-Nets Anh Dang Balaji Krishnamoorthy Manoj Iyer Presented by:
Advertisements

Design Methodology for Systems-on-Chip What is needed and what is not Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine.
A hardware-software co-design approach with separated verification/synthesis between computation and communication Masahiro Fujita VLSI Design and Education.
SoC Challenges & Transaction Level Modeling (TLM) Dr. Eng. Amr T. Abdel-Hamid ELECT 1002 Spring 2008 System-On-a-Chip Design.
Copyright  2003 Dan Gajski and Lukai Cai 1 Transaction Level Modeling: An Overview Daniel Gajski Lukai Cai Center for Embedded Computer Systems University.
Sequential Three-way Decision with Probabilistic Rough Sets Supervisor: Dr. Yiyu Yao Speaker: Xiaofei Deng 18th Aug, 2011.
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
Transaction Based Modeling and Verification of Hardware Protocols Xiaofang Chen, Steven M. German and Ganesh Gopalakrishnan Supported in part by SRC Contract.
Design Principles for Reusable, Composable and Extensible Frameworks Jilles van Gurp.
Software Testing and Quality Assurance
Mahapatra-Texas A&M-Fall'001 cosynthesis Introduction to cosynthesis Rabi Mahapatra CPSC498.
Spec-C, Handel-C, SystemC : A Comparative Study By: Nikola Rank 13 March 2006.
FunState – An Internal Design Representation for Codesign A model that enables representations of different types of system components. Mixture of functional.
Copyright  2006 Daniel D. Gajski 1 Extreme Makeover of System Design Science Daniel Gajski Center for Embedded Computer Systems (CECS) University of California,
Copyright  1999 Daniel D. Gajski IP – Based Design Methodology Daniel D. Gajski University of California
1 An Exploration of the MPEG Algorithm Using Latency Insensitive Design EE249 Presentation (12/04/1999) Trevor Meyerowitz Mentored by: Luca Carloni.
1 Ivan Lanese Computer Science Department University of Bologna Italy Concurrent and located synchronizations in π-calculus.
Transaction Level Modeling Definitions and Approximations Trevor Meyerowitz EE290A Presentation May 12, 2005.
Visual Basic Introduction IDS 306 from Shelly, Cashman & Repede Microsoft Visual Basic 5: Complete Concepts and Techniques.
Interface-based Design Donald Chai EE249. Outline Orthogonalization of concerns Formalisms Interface-based Design Example Cheetah Simulator Future Inroads.
End-to-End Design of Embedded Real-Time Systems Kang G. Shin Real-Time Computing Laboratory EECS Department The University of Michigan Ann Arbor, MI
Software Issues Derived from Dr. Fawcett’s Slides Phil Pratt-Szeliga Fall 2009.
Router modeling using Ptolemy Xuanming Dong and Amit Mahajan May 15, 2002 EE290N.
Transaction Based Modeling and Verification of Hardware Protocols Xiaofang Chen, Steven M. German and Ganesh Gopalakrishnan Supported in part by SRC Contract.
UML for Embedded Systems Development— Extensions; Hardware-Software CoDesign.
Lesson-21Process Modeling Define systems modeling and differentiate between logical and physical system models. Define process modeling and explain its.
Architectural Design Establishing the overall structure of a software system Objectives To introduce architectural design and to discuss its importance.
1 Embedded Computer System Laboratory RTOS Modeling in Electronic System Level Design.
Presenter : Cheng-Ta Wu Vijay D’silva, S. Ramesh Indian Institute of Technology Bombay Arcot Sowmya University of New South Wales, Sydney.
Web-based design Flávio Rech Wagner UFRGS, Porto Alegre, Brazil SBCCI, Manaus, 24/09/00 Informática UFRGS.
An Information Theory based Modeling of DSMLs Zekai Demirezen 1, Barrett Bryant 1, Murat M. Tanik 2 1 Department of Computer and Information Sciences,
Chapter 10 Architectural Design
Compositional IS Development Framework Application Domain Application Domain Pre-existing components, legacy systems Extended for CD (ontologies) OAD Methods.
Principles Of Digital Design Chapter 1 Introduction Design Representation Levels of Abstraction Design Tasks and Design Processes CAD Tools.
Extreme Makeover for EDA Industry
New Strategies for System Level Design Daniel Gajski Center for Embedded Computer Systems (CECS) University of California, Irvine
By Xiangzhe Li Thanh Nguyen.  Introduction  Terminology  Architecture  Component  Connector  Configuration  Architectural Style  Architectural.
Automatic Communication Refinement for System Level Design Samar Abdi, Dongwan Shin and Daniel Gajski Center for Embedded Computer Systems, UC Irvine
Model-Driven Analysis Frameworks for Embedded Systems George Edwards USC Center for Systems and Software Engineering
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
Fast Simulation Techniques for Design Space Exploration Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet
A Graph Based Algorithm for Data Path Optimization in Custom Processors J. Trajkovic, M. Reshadi, B. Gorjiara, D. Gajski Center for Embedded Computer Systems.
Overview of MOT Knowledge representation system : Basic Modeling Editor LexiconGrammarSemantics Pragmatics MOT Editor.
Lyra – A service-oriented and component-based method for the development of communicating systems (by Sari Leppänen, Nokia/NRC) Traditionally, the design,
TTCN-3 MOST Challenges Maria Teodorescu
EEE440 Computer Architecture
Submodule construction in logics 1 Gregor v. Bochmann, University of Ottawa Using First-Order Logic to Reason about Submodule Construction Gregor v. Bochmann.
1 Embedded Computer System Laboratory Systematic Embedded Software Gerneration from SystemC.
Verify 2003 System Debugging and Verification : A New Challenge Daniel Gajski Samar Abdi Center for Embedded Computer Systems University.
1 Copyright  2001 Pao-Ann Hsiung SW HW Module Outline l Introduction l Unified HW/SW Representations l HW/SW Partitioning Techniques l Integrated HW/SW.
Lecture 5 1 CSP tools for verification of Sec Prot Overview of the lecture The Casper interface Refinement checking and FDR Model checking Theorem proving.
Architecture View Models A model is a complete, simplified description of a system from a particular perspective or viewpoint. There is no single view.
Open Incremental Model Checking (OIMC) and the Role of Contracts Model-Based Programming and Verification.
Teaching The Principles Of System Design, Platform Development and Hardware Acceleration Tim Kranich
What’s Ahead for Embedded Software? (Wed) Gilsoo Kim
System-on-Chip Design Hao Zheng Comp Sci & Eng U of South Florida 1.
Software Quality and Safety Pascal Mbayiha.  software engineering  large, complex systems  functionality, changing requirements  development difficult.
Quality Assurance in the Presence of Variability Kim Lauenroth, Andreas Metzger, Klaus Pohl Institute for Computer Science and Business Information Systems.
Lecture VIII: Software Architecture
System-on-Chip Design
Software Design Methodology
Designing Software for Ease of Extension and Contraction
IP – Based Design Methodology
Model-Driven Analysis Frameworks for Embedded Systems
Introduction to cosynthesis Rabi Mahapatra CSCE617
CS223: Software Engineering
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
CprE 588 Embedded Computer Systems
Transaction Level Modeling: An Overview
Top-Down Design with Functions
Presentation transcript:

Design & Co-design of Embedded Systems Next Step: Transaction-Level Modeling Maziar Goudarzi

Today Program zThe next step toward higher abstractions ySystem-Level Modeling = Transaction-Level Modeling zWhat is TLM zTaxonomy of TLMs zSystem Design with TLMs Slides from D. Gajski invited talk at ISSS’03: D. Gajski, L. Cai, “Transaction-Level Modeling: An Overview,” Proc. of CODES+ISSS’03, California, 2003.

Copyright  2003 Dan Gajski and Lukai Cai 3 Transaction Level Modeling: An Overview Daniel Gajski Lukai Cai Center for Embedded Computer Systems University of California, Irvine lcai}

Copyright  2003 Dan Gajski and Lukai Cai 4 Acknowledgement We would like to thank transaction level team at CECS that has contributed many ideas through numerous lunch discussions: Samar Abdi Rainer Doemer Andreas Gerstlauer Junyu Peng Dongwan Shin Haobo Yu

Copyright  2003 Dan Gajski and Lukai Cai 5 Overview Motivation for TLM TLM definition TLMs at different abstraction levels TLMs for different design domains SL methodology = model algebra Conclusion

Copyright  2003 Dan Gajski and Lukai Cai 6 Motivation SoC problems Increasing complexity of systems-on-chip Shorter times-to-market SoC solutions Higher level of abstraction – transaction level modeling (TLM) IP reuse System standards TLM questions What is TLM ? How to use TLM ? This paper TLM taxonomy TLM usage

Copyright  2003 Dan Gajski and Lukai Cai 7 TLM Definition TLM = Objects Computation objects + communication objects Composition Computation objects read/write abstract (above pin-accurate) data types through communication objects Advantages Object independence –Each object can be modeled independently Abstraction independence –Different objects can be modeled at different abstraction levels

Copyright  2003 Dan Gajski and Lukai Cai 8 Abstraction Models Time granularity for communication/computation objects can be classified into 3 basic categories. Models B, C, D and E could be classified as TLMs.

Copyright  2003 Dan Gajski and Lukai Cai 9 A: “Specification Model” Objects -Computation -Behaviors -Communication -Variables Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization -Notify/Wait

Copyright  2003 Dan Gajski and Lukai Cai 10 B: “Component-Assembly Model” Objects -Computation - Proc - IPs - Memories -Communication -Variable channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization -Notify/Wait

Copyright  2003 Dan Gajski and Lukai Cai 11 C: “Bus-Arbitration Model” Objects -Computation - Proc - IPs (Arbiters) - Memories -Communication - Abstract bus channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization -Notify/Wait

Copyright  2003 Dan Gajski and Lukai Cai 12 D: “Bus-Functional Model” Objects -Computation - Proc - IPs (Arbiters) - Memories -Communication - Protocol bus channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization -Notify/Wait

Copyright  2003 Dan Gajski and Lukai Cai 13 E: “Cycle-Accurate Computation Model” Objects -Computation - Proc - IPs (Arbiters) - Memories - Wrappers -Communication - Abstract bus channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization -Notify/Wait

Copyright  2003 Dan Gajski and Lukai Cai 14 F: “Implementation Model” Objects -Computation - Proc - IPs (Arbiters) - Memories -Communication -Buses (wires) Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization -Notify/Wait

Copyright  2003 Dan Gajski and Lukai Cai 15 Characteristics of Different Abstraction Models

Copyright  2003 Dan Gajski and Lukai Cai 16 Model Algebra Algebra = [ex: a * (b + c)] Model = [ex: ] Transformation t(model) is a change in objects or compositions. Model refinement is an ordered set of transformations,, such that model B = t m ( … ( t 2 ( t 1 ( model A ) ) ) … ) Model algebra = Methodology is a sequence of models and corresponding refinements

Copyright  2003 Dan Gajski and Lukai Cai 17 Model Definition Model = Objects Behaviors (representing tasks / computation / functions) Channels (representing communication between behaviors) Composition rules Sequential, parallel, pipelined, FSM Behavior composition creates hierarchy Behavior composition creates execution order –Relationship between behaviors in the context of the formalism Relations amongst behaviors and channels Data transfer between channels Interface between behaviors and channels Copyright  2003 Dan Gajski and Samar Abdi Verify 2003

Copyright  2003 Dan Gajski and Lukai Cai 18 Rearrange object composition To distribute computation over components Replace objects Import library components Add / Remove synchronization To correctly transform a sequential composition to parallel and vice-versa Decompose abstract data structures To implement data transaction over a bus Other transformations. Model Transformations (Rearrange and Replace) a*(b+c) = a*b + a*c Distributivity of multiplication over addition B2 B3 B1 B2 B3 = Distribution of behaviors (tasks) over components analogous to…… PE1 PE2 Copyright  2003 Dan Gajski and Samar Abdi Verify 2003

Copyright  2003 Dan Gajski and Lukai Cai 19 Model Refinement Definition Ordered set of transformations is a refinement –model B = t m ( … ( t 2 ( t 1 ( model A ) ) ) … ) Derives a more detailed model from an abstract one Specific sequence for each model refinement Not all sequences are relevant Equivalence verification Each transformation maintains functional equivalence The refinement is thus correct by construction Refinement based system level methodology Methodology is a sequence of models and refinements Copyright  2003 Dan Gajski and Samar Abdi Verify 2003

Copyright  2003 Dan Gajski and Lukai Cai 20 Verification Transformations preserve equivalence Same partial order of tasks Same input/output data for each task Same partial order of data transactions Same functionality in replacements All refined models will be “equivalent” to input model Still need to verify first model using traditional techniques Still need to verify equivalence of replacements Refinement Tool t1 t2 … tm Model A Model B Designer Decisions Library of objects Copyright  2003 Dan Gajski and Samar Abdi Verify 2003

Copyright  2003 Dan Gajski and Lukai Cai 21 Synthesis Set of models Sets of design tasks Profile Explore Select components / connections Map behaviors / channels Schedule behaviors/channels. Each design decision => model transformation Detailing is a sequence of design decisions Refinement is a sequence of transformations Synthesis = detailing + refinement Challenge: define the sequence of design decisions and transformations

Copyright  2003 Dan Gajski and Lukai Cai 22 Design Domains

Copyright  2003 Dan Gajski and Lukai Cai 23 SCE: SoC Environment

Copyright  2003 Dan Gajski and Lukai Cai 24 SCE: SoC Environment (cont’d)

Copyright  2003 Dan Gajski and Lukai Cai 25 SCE: SoC Environment (cont’d)

Copyright  2003 Dan Gajski and Lukai Cai 26 SCE: SoC Environment (cont’d)

Copyright  2003 Dan Gajski and Lukai Cai 27 SCE Experiment is Very Positive Source:

Copyright  2003 Dan Gajski and Lukai Cai 28 Conclusion Computation and communication objects of TLM are connected through abstract data types TLM enables modeling each component independently at different abstraction levels The major challenge is to define necessary and sufficient set of models for a design flow The next major challenge is to define model algebra and corresponding methodology for each application such that algorithms and tools for modeling, verification, exploration, synthesis and test can be easily developed Opportunities are bigger than anything seen before

Today Summary zThe key enabling concept: channels zNext session: ySystemC 2.0 facilities to define channels (and hence, to support Transaction-Level Modeling)