Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.

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Presentation transcript:

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Pseudo-nMOS n Uses a p-type as a resistive pullup, n-type network for pulldowns.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Characteristics n Consumes static power. n Has much smaller pullup network than static gate. n Pulldown time is longer because pullup is fighting.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Output voltages n Logic 1 output is always at V DD. n Logic 0 output is above Vss. n V OL = 0.25 (V DD - V SS ) is one plausible choice.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Producing output voltages n For logic 0 output, pullup and pulldown form a voltage divider. n Must choose n, p transistor sizes to create effective resistances of the required ratio. n Effective resistance of pulldown network must be comptued in worst case—series n- types means larger transistors.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Transistor ratio calculation n In steady state logic 0 output: –pullup is in linear region,V ds = V out - (V DD - V SS ) ; –pulldown is in saturation. n Pullup and pulldown have same current flowing through them.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Transistor ratio, cont’d. n Equate two currents: –I dp = I dd. n Using 0.5 mm parameters, 3.3V power supply: –W p /L p / W n /L n = 3.9.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf DCVS logic n DCVSL = differential cascode voltage logic. n Static logic—consumes no dynamic power. n Uses latch to compute output quickly. n Requires true/complement inputs, produces true/complement outputs.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf DCVS structure

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf DCVS operation n Exactly one of true/complement pulldown networks will complete a path to the power supply. n Pulldown network will lower output voltage, turning on other p-type, which also turns off p-type for node which is going down.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf DCVS example

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Precharged logic n Precharged logic uses stored charge to help evaluation. n Precharge node, selectively discharge it. n Take advantage of higher speed of n-types. n Requires multiple phases for evaluation.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Domino logic n Uses precharge clock to compute output in two phases: –precharge; –evaluate. n Is not a complete logic family—cannot invert.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Domino gate structure

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Domino phases Controlled by clock . n Precharge: p-type pullup precharges the storage node; inverter ensures that output goes low. n Evaluate: storage node may be pulled down, so output goes up.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Domino buffer n Output inverter is needed for two reasons: –make sure that outputs start low, go high so that domino output can be connected to another domino gate; –protects storage node from outside influence.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Domino operation

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Domino effect Gate outputs fall in sequence: gate 1gate 2gate 3

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Monotonicity n Domino gates inputs must be monotonically increasing: glitch causes storage node to discharge.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Output buffer n Inverting buffer isolates storage node. Storage node and inverter have correlated values.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Using domino logic n Can rewrite logic expression using De Morgan’s Laws: –(a + b)’ = a’b’ –(ab)’ = a’ + b’ n Add inverters to network inputs/outputs as required.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Domino and stored charge n Charge can be stored in source/drain connections between pulldowns. n Stored charge can be sufficient to affect precharge node. n Can be averted by precharging the internal pulldown network nodes along with the precharge node.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Design-for-yield n Design processes that improve chip yield in very deep submicron/nanometer technologies. n Must treat design and manufacturing as a unified processing to maximize yield in nanometer technologies.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Variations in manufacturing n Three types of variations: –Systematic variations can be predicted based on design and mask information plus manufacturing equipment. –Random variations include variations in parameters, etc. –Environmental variations include temperature, etc.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Trends in manufacturing n Larger variations in process and circuit parameters. n Higher leakage currents. n Patterning problems caused by specific combinations of geometric features. n Metal width and thickness variations. n Stress in vias.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Design-for-yield examples n Lithographic simulation to find yield problems not covered by standard design rules. n Extra vias added to increase the reliability of connections. n Statistical timing analysis to identify problems caused by variations in wiring.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Gates as IP n The standard cell library was one of the first forms of IP. –Reusable across many chips. –Portable from one process to another. n Standard cell compatibility issues: –Layout: cell size, pin placement. –Delay: driving specified load. –Power consumption.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Standard cell physical design n Basic cell organization is dictated by placement and routing system. n All cells are the same height. –May be one of a set of standard widths. n Pins must be placed on routing grid, usually determined by wiriing layers used.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Standard cell logical design n Must support a Boolean complete set of functions. n Should support enough gate types for good logic synthesis results. n Need several electrical variations of each function: –Low power. –High speed.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Cell verification and qualification n Cells are verified by layout extraction and circuit simulation. –Simulate a variety of process parameter combinations. n Qualification requires fabrication of cells on the target process.