Boolean Algebra

Combinational-Circuit Analysis We analyze a combinational logic circuit by obtaining a formal description of its logic function. Once we have a description of the logic function: we can determine the behaviour of the circuit for various input combinations. We can manipulate the algebraic description to suggest different circuit structure. We can convert to sum-of-products expression for PLDs. We can use to analyze a larger system that includes it.

Combinational analysis There are a number of ways to obtain a formal description of the circuit’s function.

Obtaining truth table Produce output from different input combinations ( 2 n ).

Signal expressions Multiply out: F = ((X + Y’). Z) + (X’. Y. Z’) = (X. Z) + (Y’. Z) + (X’. Y. Z’)

New circuit, same function

“Add out” logic function Circuit:

Boolean function as a sum of minterms: Any Boolean function can be expressed as a canonical sum. The canonical sum of a logic function is a sum of the minterms corresponding to truth-table rows for which the function produces a 1 output F =  x,y,z (0,1,2,5,7) = X’.Y’.Z’ + X’.Y’.Z + X’.Y.Z’ + X.Y’.Z + X.Y.Z

Boolean function as a pruduct of maxterms: Any Boolean function can be expressed as a canonical pruduct. The canonical pruduct of a logic function is a pruduct of the maxterms corresponding to truth-table rows for which the function produces a 0 output F =  x,y,z (0,3,4,6) = (X+Y+Z). (X+Y’+Z’). (X’+Y+Z). (X’+Y’+Z)

Shortcut: Symbol substitution

Different circuit, same function

Another example

Circuit Descriptions and Designs What is the starting point for designing combinational logic circuit? Usually, we are given a word description of a problem occasionally, the description is a list of input combinations (ON, OFF), the verbal equivalent of a truth table or the canonical sum or product.

Combinational-Circuit Analysis Combinational circuits -- outputs depend only on current inputs (not on history). Kinds of combinational analysis: –exhaustive (truth table) –algebraic (expressions) –simulation / test bench Write functional description using schematic editor Write functional description in HDL Define test conditions / test vecors, including corner cases Compare circuit output with functional description (or known- good realization) Repeat for “random” test vectors

Example, 4-bit prime number detector Given a 4-bit input combination N = N 3 N 2 N 1 N 0, this function produces a 1 output for N = 1, 2, 3, 5, 7, 11, 13 and 0 otherwise. A logic function described in this way can be designed directly from the canonical sum or product expression i = AB CDEF F =  N 3 N 2 N 1 N 0 (1, 2, 3, 5, 7, 11, 13) = N’ 3 N’ 2 N’ 1 N 0 + N’ 3 N’ 2 N 1 N’ 0 + N’ 3 N’ 2 N 1 N 0 + …

Design from truth table Truth table --> canonical sum (sum of minterms) Example: prime-number detector –4-bit input, N 3 N 2 N 1 N 0 row N 3 N 2 N 1 N 0 F F =   (1,2,3,5,7,11,13)

Minterm list --> canonical sum

Algebraic simplification Theorem T8, Reduce number of gates and gate inputs

Reduced circuit

Combinational-Circuit Design Sometimes you can write an equation or equations directly using “logic” (the kind in your brain). Example (alarm circuit): Corresponding circuit:

Simple Example Sometimes you can write an equation or equations directly using “logic” (the kind in your brain). Example (alarm circuit): Door Open = 1, Key Left = 1 WARNING = DOOR. KEY C = A. B Corresponding circuit:

Circuit Descriptions and Designs The alarm output is 1 if the PANIC input is 1, or if the ENABLE input is 1, the EXITING input is 0, and the house is not secure; the house is secure if the WINDOW, DOOR, and GARAGE inputs are all 1. ALARM = PANIC + ENABLE. EXITING’. SECURE’ SECURE = WINDOW. DOOR. GARAGE ALARM = PANIC + ENABLE. EXITING’. (WINDOW. DOOR. GARAGE)’

Alarm Circuit

Modified Alarm Function “Multiply out”: ALARM = PANIC + ENABLE. EXITING’. (WINDOW. DOOR. GARAGE)’ ALARM = PANIC + ENABLE. EXITING’. (WINDOW’ + DOOR’ + GARAGE’) ALARM = PANIC + ENABLE. EXITING’. WINDOW’ + ENABLE. EXITING’. DOOR’ + ENABLE. EXITING’. GARAGE’

Alarm-circuit transformation Sum-of-products form –Useful for programmable logic devices (PLDs)

Circuit transformation The design methods that we have described so far use AND, OR, and NOT gates. We might like to use NAND and NOR gates, too because - they are faster than ANDs and ORs in most technologies. But we develop a logic expression from normal logic (ANDs and ORs) and then we translate it into other forms using NAND and NOR gates. –An AND-OR (sum-of-products) circuit may be converted to a NAND-NAND circuit, and –a OR-AND (product-of- sums) circuit may be converted to a NOR-NOR circuit.

Sum-of-products form AND-OR NAND-NAND

Product-of-sums form OR-AND NOR-NOR P-of-S preferred in CMOS, TTL (NAND-NAND)