Princess Sumaya Univ. Computer Engineering Dept. Chapter 3:

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Signed Number Representations  Sign-Magnitude Example: + 5 = – 5 = Range:  2’s Complement Example: + 5 = – 5 = S Magnitude –7 ≤ N ≤ +7–(2 n –1 –1) ≤ N ≤ +(2 n –1 –1) 0 Magnitude 1 2’s Complement 1 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Signed Number Representations  2’s Complement Range: Exercise: Calculate the range for 8 bits –(2 n –1 ) ≤ N ≤ +(2 n –1 –1) 8 Combinations 2 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept.  Used to represent integers, both positive & negative  Distinguish: “2’s Comp. System” from “2’s Comp. Operation” Example: Represent the number +5 in 2’s Comp. System Correct:Incorrect: +5 = ( ) 2 ( ) 2 2’s Complement System 3 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. 2’s Complement System Example: Given a number represented in 2’s comp. system, write an algorithm to square it. Answer 1) 2) 3) 4 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept.  Bit-by-bit addition, with carry propagation.  Unsigned Binary Operands: ●Produces unsigned binary ●Possible overflow (Cy = 1)  Signed 2’s Comp. Operands: ●Produces 2’s complement ●Possible overflow C y  C y-1 +. Addition / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. –. . +. Subtraction  2’s Complement Addition  Unsigned Binary Operands: ●If Cy = 1, result is unsigned binary ●If Cy = 0, result is negative (2’s comp) ●No overflow  Signed 2’s Comp. Operands: ●Produces 2’s complement ●Possible overflow C y  C y-1 –.  / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. × Multiplication  Bit-by-bit Multiplication  Unsigned Binary Operands ●Unsigned result ●2n-bit result from n × n bits operands ●No overflow ●Partial Sum × Partial Sum = 7 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication Multiplicand Product Multiplier × Control Unit ALU 8 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication Multiplicand Product Multiplier Control Unit 0 1 Add Load × ALU 9 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication Multiplicand Product Multiplier 0 1 Control Unit Shift Left Shift Right 1 1 × ALU 10 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication Multiplicand Product Multiplier 1 1 × Shift Left Shift Right Control Unit ALU 11 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication Multiplicand Product Multiplier 1 1 × Add Load Shift Left Shift Right Control Unit ALU 12 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication Multiplicand Product Multiplier 1 1 × Shift Left Shift Right Control Unit ALU 13 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication Multiplicand Product Multiplier 1 1 × Control Unit  Delay: Number of Clocks =.... Clocks ALU 14 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication M M M M Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit m m ALU Clock 15 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication M M M M p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit 0 m m m ALU Clock 16 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication 0 0 M M M M p p p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit 0 0 m m ALU Clock 17 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication 0 M M M M p p p p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit m ALU Clock 18 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Multiplication M M M M p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit ALU Clock 19 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Multiplication  ALU Size? 20 / × Partial Sum Partial Sum: Partial Sum Partial Sum: Partial Sum Partial Sum: Partial Sum Partial Sum: :03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Signed Multiplication  Signed 2’s Comp. Operands: ●Convert negative operands to positive values ●Perform unsigned multiplication ●Negate the result if the two operands differ in sign 21 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Division  Subtract Divisor & Drop a Bit  Unsigned Binary Operands ●Unsigned result ●2n-bit Dividend by n-bit divisor  n-bit quotient and n-bit remainder ●Possible overflow (big quotient) ♦ Divide by zero ♦ Quotient ≥ 2 n.. │ / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder (Dividend) Quotient 0 0 Control Unit ALU │ – – – – – / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder (Dividend) Quotient 0 0 Control Unit ALU │ – – – – – Subtract Load 24 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient 0 0 Control Unit ALU │ – – – – – Add Load Shift Left 0 Shift Right 25 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient 0 0 Control Unit ALU │ – – – – – Subtract Load 26 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient 0 0 Control Unit ALU │ – – – – – Shift Left 1 Shift Right 27 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient Control Unit ALU │ – – – – – Subtract Load 28 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient Control Unit ALU │ – – – – – Shift Left 1 Shift Right 29 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient Control Unit ALU │ – – – – – Subtract Load 30 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient Control Unit ALU │ – – – – – Add Load Shift Left 0 Shift Right 31 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient Control Unit ALU │ – – – – – Subtract Load 32 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient Control Unit ALU │ – – – – – Shift Left 1 Shift Right 33 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Sequential Division Divisor Remainder Quotient Control Unit ALU │ – – – – – How many times was the Divisor & Quotient shifted? How many clocks? 34 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Signed Division  Signed 2’s Comp. Operands: ●Convert negative operands to positive values ●Perform unsigned division ●Negate the result (?) if the two operands differ in sign ♦ Which result? Quotient or remainder or both? ●Dividend = Quotient × Divisor + Remainder ♦ Example: 16 ÷ 3 ●Rule: Dividend & Remainder must have the same sign 35 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Floating Point  Scientific Notation Example: (10.5 × 10 – 7 is not good)  Normalized Scientific Notation Example: (0.105 × 10 – 5 is not good)  Binary Numbers Example: ( × 2 – 5 is not good) (Normalized). × 10. × 2 36 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Floating Point  Sign & Magnitude  Overflow: The exponent is too large to be represented  Underflow: The exponent is too small to be represented  Single & Double Precision. × 2± S Exponent Fraction 32 bits ± ? 37 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. IEEE 754 Floating Point Standard  Single Precision:  Biased Exponent S Exponent Fraction 32 bits 1 bit 8 bits 23 bits = (biased by 127) 0 + – 38 / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. IEEE 754 Floating Point Standard  Implicit ‘1’ 1.01 × 2 0 Examples: 75 = – 0.75 = 0.0 = ? S Exponent Fraction This bit is always 1 No need to store it, hence implicit ( ) – ( ) / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. IEEE 754 Floating Point Standard  Reserved Bit Patterns ●Zero: ●± Infinity: ●Others like denormalized number and Not-a-Number / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Floating-Point Addition / Subtraction  Need to Align Decimal Points Example: Add Normalized Forms: Align Decimal Point: Perform Addition: Normalize Result: 0.5 = ( ) 2 = = ( ) 2 = 0 × 2 – / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Floating-Point Multiplication  Need to Account for Biased Exponents Example: Multiply 0.5 × Normalized Forms: Multiply Fractions: Add Exponents: Sub Extra Bias: Round & Normalize: 0.5 = ( ) 2 = = ( ) 2 = × – / 41 11:03 AM

Princess Sumaya University – Computer Organization & Design Computer Engineering Dept. Chapter 3