Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D New Product Introduction: High-Performance 4-PLL Clock Generator Cypress Delivers Industry-Leading Flexible Timing Solutions for Next-Generation Consumer Devices

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Consumer devices are becoming feature-rich and connected They integrate storage, media processing and connectivity to enhance the user experience So users can create, store and share digital media content anywhere and anytime Sharing high-resolution media content requires faster data transfer standards The data storage transfer protocol has moved from SATA 1.0 to SATA 3.0 Ethernet systems have migrated from 10 Gbps to 100 Gbps USB 3.0 is replacing USB 2.0 for user connectivity Data interconnect standards are moving from PCIe 1.0 to PCIe 3.0 Consumer devices must support multiple data standards, each with specific timing requirements Consumer devices require highly integrated and flexible timing solutions Consumer Devices Are Driving Faster Data Transfer Standards CY Reference Clocks for Data Transfer Standards 1 CY27410 programmable clock generator can generate up to 12 output frequencies 2 Cycle-to-Cycle Jitter 3 High-speed current steering logic PCIe 3.0 Hub Ethernet MAC SATA 3.0 Host USB 3.0 Hub 100-MHz LVDS, 3-ps RMS Jitter 48-MHz LVCMOS, 100-ps CCJ 2 25-MHz LVCMOS, 100-ps CCJ MHz HCSL 3, 1-ps RMS Jitter 24 MHz CY a

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Cypress, the leader in programmable clocks for nearly two decades, designed the world’s first: Programmable clock generator Programmable skew buffer Programmable die for crystal oscillators Cypress has a broad clock portfolio 1,700 clock marketing part numbers Clock generators that generate frequencies up to 700 MHz with <0.6-ps RMS Phase Jitter Clock buffers that support frequencies up to 1,500 MHz with <0.05-ps RMS Phase Jitter Industrial- and automotive-grade products Cypress is a proven and reliable clock supplier that has sold over 2.5 billion units Offers predictable lead times of ≤6 weeks with greater than 99.4% on-time delivery Ensures a stable supply for its customers with multiple assembly and test sites Supports legacy parts >20 years old Pioneer in Programmable Clock Solutions 3b

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Terms You Will Hear Today Cycle-to-Cycle Jitter (ps) The maximum difference in a clock period between two adjacent clock cycles, measured over 1,000 clock cycles Phase Noise (dBc/Hz) Noise power relative to clock signal power, measured in a 1Hz window centered at a given offset frequency from the clock signal RMS Phase Jitter (ps) The integration of Phase Noise over a specified bandwidth, most commonly 12 kHz to 20 MHz (see below) RMS Phase Jitter =, where f c is the clock frequency Voltage Controlled Frequency Synthesis (VCFS) A method by which the frequency of a clock signal is varied based on a control voltage input Phase Noise Plot Frequency (kHz) Offset 1-Hz BW Power (dBc) Phase Noise (dBc/Hz) RMS Phase Jitter Plot Frequency (kHz) Phase Noise (dBc/Hz) f 1 Phase Noise PN (f) f c f c 4a f 2 RMS Phase Jitter

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Terms You Will Hear Today Electromagnetic Interference (EMI) A disturbance that affects an electrical circuit, often caused by electromagnetic radiation emitted by an external source Clocks create electromagnetic radiation, because of their high frequency and periodic nature Spread Spectrum (SS) Modulation A method used to vary the frequency of a clock signal to spread its energy across a wider frequency range, thus reducing EMI Frequency Select A feature in a clock generator used to select a preprogrammed output frequency using external digital control pins Used also to selectively turn off the reference frequencies to certain peripherals to reduce power consumption Glitch An undesired transition that occurs before the clock signal settles into its intended value Glitches Glitch Time (ps) Volts (V) SS Modulation in the Frequency Domain Power (dBc) Frequency (kHz) SS EMI Reduction: Typically 10 dB Using a crystal-based solution Using a crystal + CY EMI-reduction clock FCC EMI Limit 4b

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Design Problems Engineers Face Multiple clocks in consumer devices increase the BOM cost and PCB area Up to 12 reference clocks, including RTC 1, may be required for the processors and peripherals (PCIe, USB, SATA, GbE) High-frequency clocks produce enough EMI to violate regulatory emission standards Traditional EMI-reduction solutions, such as ferrite beads and chokes, are expensive and add board space EMI problems threaten time-to-market because EMI testing is typically performed at the end of the development cycle Consumer products require additional components to manage reference clocks Audio systems require Glitch-free clock switching to suppress burst noise 2 Multifunction printers need to selectively turn off clocks to certain peripherals to reduce power consumption Consumer devices with multiple systems-on-chip require their respective reference clocks to be in phase with each other Cypress’s CY PLL clock generator solves these problems Saves board space by generating up to 12 programmable output frequencies on a single chip Reduces EMI using SS Modulation Simplifies system design with Glitch-free switching, Frequency Select and early/late clocks for phase control Cypress’s high-performance clock generator is a single-chip solution that simplifies system design 5 1 Real-time clock ( kHz) 2 Audible noise caused by high-frequency Glitches that occur during frequency switching

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction Rev *D FeatureCY274xx5P49V5901ASi5338 VCFS YesNo Cascading PLL YesNo Zero Delay Buffer Mode YesNoYes Non-Zero Delay Buffer Mode Yes Early/Late Phase Clock YesNoYes Glitch-Free Outputs Yes Frequency Select Yes No On-Board Programming Yes Low frequency outputs YesNo D + C V 7a CY27410 vs. Competition

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction Rev *D Max. O/P Freq. (single-ended) 250 MHz200 MHz Max. O/P Freq. (differential) 700 MHz350 MHz710 MHz Cycle-to-Cycle Jitter 30 ps 29 ps RMS Phase Jitter 0.7 ps Number of Outputs 12 Single-Ended, 8 Differential8 Single-Ended, 4 Differential Current per PLL 20 mA30 mA45 mA SS (center) ±0.05% to ±2.50%±0.25% to ±2.50%±0.1% to ±5% SS (down) -0.1% to -5.0%-0.5% to -5.0% -0.1% to 5.0% Temperature Grade Industrial and AEQ-100 (-40ºC to +85ºC) Industrial (-40ºC to +85ºC) FeatureCY274xx5P49V5901ASi5338 D + C CY27410 vs. Competition 7b

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D The CY27410 Is a Better Solution And other components such as RTC and buffers Simplify a conventional design using multiple timing components… By selecting Cypress’s multi-output programmable clock… To produce an integrated, low-cost timing solution for multiple applications. With ferrite beads and chokes to reduce EMI Separate chip for each data transfer standard PCIe Clock10GbE Clock Multifunction Printer Car Infotainment System Femtocell 10GbE Real-Time Clock ( RTC)Clock Buffer 4-PLL Clock Generator Reference clocks for PCIe, SATA, GbE and USB Spread Spectrum Modulation to reduce EMI Low-frequency support for RTC Configurable as zero or non-zero delay buffer 6

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Clock GeneratorsClock Buffers EMI ReductionNon-EMI ReductionZero Delay Buffer (ZDB)Non-Zero Delay Buffer (NZDB) Standard Performance High Performance Application Specific Timing Solutions Portfolio (NDA) Programmable | High-Performance | EMI Reduction | Automotive CY2429x Max. Frequency: 200 MHz 2-4 outputs; PCIe ps CCJ 4 ; Ind 2 CY24293A Max. Frequency: 200 MHz 2 outputs; 1 PLL; PCIe ps CCJ 4 ; Auto A 3 CY22050/150 Max. Frequency: 200 MHz 3-6 outputs; 1 PLL 250-ps CCJ 4 ; Ind 2 CY2239x/CY229x/CY2238x Max. Frequency: 200 MHz 3-6 outputs; 3-4 PLL; I 2 C 400-ps CCJ 4 ; Ind 2 ; Auto E 5 CY2Xx (FleXO™) Max. Frequency: 690 MHz 1 output; Frequency Margining 0.6-ps RMS Jitter 1 ; Ind 2 CY254x/CY251x Max. Frequency: 166 MHz 3-9 outputs; 1-4 PLL; I 2 C 100-ps CCJ 4 ; Ind 2 CY274x Max. Frequency: 700 MHz 12 outputs; PCIe 3.0; 4 PLL 0.7-ps RMS Jitter 1 ; Ind 2 ; Auto A 3 CY7B99x (RoboClock™) Max. Frequency: 200 MHz 8-18 outputs; Configurable Skew 50-ps CCJ 4 ; Ind 2 CY23S02/05/08/09/FP12 Max. Frequency: 200 MHz 2-12 outputs; Spread Aware 200-ps CCJ 4 ; Ind 2 CY23FS04/08 Max. Frequency: 200 MHz 4-8 outputs; Fail Safe ps CCJ 4 ; Ind 2 CY230x/EP0x Max. Frequency: 220 MHz 5-9 outputs; LVCMOS 22-ps CCJ 4 ; Ind 2 ; Auto A 3 CY2DLx/DMx/DPx/CPx Max. Frequency: 1.5 GHz 2-10 outputs; LVDS, LVPECL, CML 0.05-ps RMS Jitter 1 ; Ind 2 CY230xNZ Max. Frequency: 133 MHz 4-18 outputs; LVCMOS 250-ps CCJ 4 ; Ind 2 4 Cycle-to-cycle jitter 5 AEC-Q100: -40ºC to +125ºC 6 Automatic clock switching on failure of a clock source 1 Integrated phase noise across 12-kHz to 20-MHz offset 2 Industrial grade: -40ºC to +85ºC 3 AEC-Q100: -40ºC to +85ºC CY294x/ CY5107 Max. Frequency: 2.1 GHz 1 output; 40/100 GbE; 1 PLL 0.15-ps RMS Jitter 1 ; Ind 2 CY276x Max. Frequency: 700 MHz 8 outputs; PCIe 3.0, 10GbE; 2 PLL 0.7-ps RMS Jitter 1 ; Ind 2 ; Auto A 3 CY278x Max. Frequency: 200 MHz 4 outputs; PCIe 3.0; 1 PLL < 0.7-ps RMS Jitter 1 ; Ind 2 ; Auto A 3 CY22800/801 Max. Frequency: 166 MHz 3 outputs; 1 PLL 250-ps CCJ 4 ; Ind 2 ProductionDevelopment QQYY Availability Sampling Concept Status NEW Q115 Q315 Q115

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Product Overview Multifunction printers Digital TVs Blu-ray recorders Home gateways Femtocells Routers and switches Applications High frequency: 700-MHz differential, 250-MHz single-ended Pin select and I 2 C programming Twelve outputs: Eight configurable as differential or single-ended Four single-ended Reference clock support for PCIe 3.0, SATA 2.0 and 10 GbE RMS Phase Jitter <0.7 ps (typical) Additional features: Configurable as zero or non-zero delay buffer Glitch-free frequency switching Frequency Select Early/ late clocks PLL cascading Voltage Controlled Frequency Synthesis Features Preliminary Datasheet: Contact SalesContact Sales Collateral Sampling: Now Production:Q Availability 1 Crystal input 2 Crystal output 3 Reference clock inputs 4 Serial port 5 Voltage input pin for VCFS 6 Frequency Select inputs Memory and Control Logic Out1 Out2 Out3P Out3N Out4P Out4N Out5P Out5N Out6P Out6N XIN 1 XOUT 2 IN1P 3 IN1N 3 IN2P 3 IN2N 3 Four-PLL Spread-Spectrum Clock Generator PLL Input Block Out7P Out7N Out8P Out8N Out9P Out9N Out10P Out10N Out11 Out12 Divider PLL 1 Block PLL 3 Block PLL 2 Block PLL 4 Block Output Bank 2 Output Bank 1 Block Diagram SCLK 4 SDAT 4 VIN 5 FS2 6 FS1 6 FS0 6 11

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D 1.Visit the Cypress Timing Solutions website: 2.See our roadmap for Timing Solutions: 3.Request a preliminary datasheet: Contact SalesContact Sales 4.Contact us for questions: Here’s How to Get Started 12

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D APPENDIX 15

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D Product Selector Guide Part NumberNo. of OutputsProgrammabilityGradePackage CY27410FLTXI12FieldIndustrial48-QFN CY27410LTXI - XXX12FactoryIndustrial48-QFN CY27430FLTXA 9FieldAutomotive48-QFN CY27430LTXA - XXX 9FactoryAutomotive48-QFN CY 274 XX F LTX X - XXX Part Numbering Decoder Configuration identifier: Blank = Field programmable, XXX = Factory programmed Grade: I = Industrial, A = Automotive Package Type: Pb-free QFN Programmability: F = Field programmable, Blank = Factory programmed Product Type: 10 = Industrial, 30 = Automotive Marketing Code: 274 = Clock Generators Company ID: CY = Cypress 16

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Customer) Rev *D References and Links Cypress Timing Solutions Website: Timing Solutions Roadmap: Product Overview: Programming and Evaluation Kits: Software: Application Notes: Contact us for questions: 18

Owner: PAJEHigh-Performance 4-PLL Clock Generator New Product Introduction (Distributor) Rev *D System BOM 1 CY P49V5901A000NLGI SI5338M-B-GMR Clock Generator $ 7.50$5.89$8.80 Additional Single-Ended Outputs Additional Differential Outputs VCFS/Glitch-Free Outputs Low-Frequency Support Total System Cost $7.50$11.56$13.99 Savings by using CY %46% 1 1ku Digikey pricing on 07/30 /2014 (SL15300 price is for 2.5ku) 2 IDT5P49V5901A can generate eight LVCMOS frequencies and needs IDT5V19EE403NLG18 to generate the remaining four LVCMOS frequencies to match CY27410 SI5338 can generate eight LVCMOS frequencies and needs SL15300ZCT to generate the remaining four LVCMOS frequencies to match CY IDT5P49V5901A can generate four differential frequencies and needs IDT74FCT3807DCGI to generate the remaining four differential frequencies to match CY27410 SI5338 can generate four differential frequencies and needs SI52144-A01AGM to generate the remaining four differential frequencies to match CY SI5338 requires SI5351A-B-GT to provide VCFS and glitch-free outputs 5 IDT and SiLabs require an external crystal MC K-A0:ROHS (1ku pricing) to support low-frequency RTC outputs ( kHz) 8 CY27410 Value vs. Competition