P225/MAPLD 2004Pimentel1 Julio C. G. Pimentel Hoang Le-Huy Gilbert Sybille LEEPCI - Laboratory of Electro-technology, Power Electronics and Industrial Control An FPGA-Based Real Time Power System Simulator for Power Electronics

P225/MAPLD 2004Pimentel2 Plan  Introduction  Proposed Approach  Implementation Flow  Library of Components  Experimental Results  Conclusion

Pimentel3B225/MAPLD 2004 Introduction

P225/MAPLD 2004Pimentel4 Objective  Simulate in real time electrical networks including: Switched mode circuits Control circuits (controllers, modulators, etc.) Linear circuits (filters, capacitors, inductors, etc.) Non linear circuits (diodes, IGBTs, Thyristors, saturate inductors, etc.)

P225/MAPLD 2004Pimentel5 Applications  Power system stability analysis  High frequency switched converters  High frequency motion control applications: Industrial machines Hybrid vehicles  Many more …

P225/MAPLD 2004Pimentel6 Evolution of Real Time Power System Simulators  Continue Time Models  Amplifiers and passive devices  Reduced scale models Transient Network Analyzers (1970) Hybrids Digital Computers (1990)  Discrete Time Models  Parallel processors  Matrix Representation  Interactive Numeric Methods (algorithm) Proposed Approach  Hardware Emulation  FPGAs + VHDL  DSP or  Processor

Pimentel7B225/MAPLD 2004 Proposed Approach

P225/MAPLD 2004Pimentel8 General Architecture Decouple the electrical network in two parts: Decouple the electrical network in two parts: 1. Linear part - RLC network is modelled as a matrix and processed by a microprocessor 2. Nonlinear part – nonlinear devices are modelled as VHDL sub-circuits and processed in the FPGA Voltage and currents calculated by each part are exchanged at the end of each time step Voltage and currents calculated by each part are exchanged at the end of each time step

P225/MAPLD 2004Pimentel9 Data Flow Processing Model  The sub-circuits are interconnected through their input and output ports  The inputs of a sub-circuit can only change at the end of a time step  The outputs of a sub-circuit only depends on its inputs  At the end of a time step the sub-circuit transfers its calculated voltages and currents to the next sub-circuit  The sub-circuits are modelled in VHDL and implemented in a FPGA

P225/MAPLD 2004Pimentel10 The synchronization Problem The sub-circuits I/O signals can be: The sub-circuits I/O signals can be: –Control signals: CLK, RST, EN, STC, EOC and REG –Voltages and currents – fixed point integer –Logical signals: carry On/OFF information (PWM outputs, RST CLK Voltages EN STC EOC Reg Logical Signals Sub Circuit Currents Voltages Currents Logical Signals

P225/MAPLD 2004Pimentel11 The synchronization Problem (cnt’d) RST CLK EOC1 EOC2 EOCn Master State Machine The control signals are: The control signals are: –Generated by a master state machine that synchronizes the whole system –Sent to all VHDL sub-circuits The SM controls: The SM controls: –Initialization - Stability depends a lot on the initialization strategy –Sequencing 1.Send data to/from DAC 2.Send data to/from uP 3.Process data EN STC_l STC_nl REG_l REG_nl

P225/MAPLD 2004Pimentel12 I(t-1)Vb(t-1) Z -1 Decoupling Strategy Decouple the linear and nonlinear parts by introducing a Voltage-Current pair => reduce the size of the problem Decouple the linear and nonlinear parts by introducing a Voltage-Current pair => reduce the size of the problem Problem: the value of I et Vb used in each part are delayed by one time step => system may become unstable Problem: the value of I et Vb used in each part are delayed by one time step => system may become unstable ?

P225/MAPLD 2004Pimentel13 Decoupling Strategy (cnt’d) ?

P225/MAPLD 2004Pimentel14 Decoupling Strategy (in parallel) SourcesNonlinear linear Z -1 AC, DC, Sin, Pulse, Step, etc. Diode, Thyristor, MOSFET, Control, etc. State Space Model [A, B, C, D] VHDL ALGORITHM Total: 2 time step delay

P225/MAPLD 2004Pimentel15 Decoupling Strategy (in series) Total: ONLY 1 time step delay (more stable) SourcesNonlinear linear Z -1 AC, DC, Pulse, Step, etc. Diode, Thyristor, MOSFET, Control, etc. State Space Model [A, B, C, D] VHDL ALGORITHM Zero Delay The simulation of the nonlinear part takes much less than 1 us

Pimentel16B225/MAPLD 2004 Implementation Flow

P225/MAPLD 2004Pimentel17 Implementation Flow Translate PSB To VHDL Elaboration Synthesis Placement Routing FPGA Programming PSB/Matlab Schematic Library of Components For DRTPSS Vendor Library FPGA Design Flow DRTPSS Simulator

Pimentel18B225/MAPLD 2004 Library of parameter-driven components  Sources: DC, ramp, sinus, etc.  1and 3PWM modulators  PI and PID controllers  DQ-ABC and ABC-DQ converters  Components (diode, MOST, Thyristor, etc.)  Digital filters and CORDIC  D/A converters

P225/MAPLD 2004Pimentel19 Sinusoidal source n, nc, VMax Sin_1Ø clk clock out n Freq n en The sinusoidal source (example):  Can generate a sinus with 16-bit resolution (amplitude and phase)  Approximation: series of Taylor (can also use a lookup table):  Implemented using multiply-accumulate operations  Distortion < 1%

P225/MAPLD 2004Pimentel20 PWM Modulator The PWM modulator (example) Resolution: ex.: 8 bitsResolution: ex.: 8 bits frequency: 2.99 Mhzfrequency: 2.99 Mhz Modulation factor: 25%Modulation factor: 25% n PWM_1Ø en ld clkclock out input n load enable

P225/MAPLD 2004Pimentel21 3  sinusoidal PWM Modulator clock out_A n Freq n out_B n out_C n n,nc,VMax Sin_3Ø clk en EN DQ C R PWM_1Ø En Ld clk out_A n EN DQ C R PWM_1Ø En Ld clk out_B n EN DQ C R PWM_1Ø En Ld clk out_C n clock Sin_1Ø clk n Freq n State machine clk

Pimentel22B225/MAPLD 2004 Experimental Results

P225/MAPLD 2004Pimentel23 Ex1: Full Wave Rectifier PSB FPGASim FPGASim – proposed simulator (real time simulator)FPGASim – proposed simulator (real time simulator) PSB – Power System Blockset of Matlab (non real time simulator)PSB – Power System Blockset of Matlab (non real time simulator)

P225/MAPLD 2004Pimentel24 Ex2: Thyristor Rectifier FPGASim PSB

P225/MAPLD 2004Pimentel25 Ex3: Effect of Transitory on a DC-DC Buck Converter FPGASim PSB

P225/MAPLD 2004Pimentel26 Ex4: DC-DC Buck Converter with PI Controller L1=20mH R=20 C=30uF Kp=0.1 Ki=4 FPGASim PSB

P225/MAPLD 2004Pimentel27 Ex5: Three-phase DC-AC PWM Converter FPGASim PSB

P225/MAPLD 2004Pimentel28 Ex6: 50Hz – 60Hz Cicloconverter Vpeak=150V Ls=100uH Vc=100uF Rl=10Ohm Ll=100mH FPGASim PSB

Pimentel29B225/MAPLD 2004 Conclusion

P225/MAPLD 2004Pimentel30 FPGA Used  Xilinx 2VP30 Virtex II PRO Logic Cells (1): 30,816 Slices: 13, X 18 Bit Multiplier Blocks: 136 Maximum User I/O Pads: 644 PowerPC Processor Blocks: 2 (1) Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic Device RocketIO Transceiver Blocks PowerPC Processor Blocks Logic Cells(1) CLB (1 = 4 slices = max 128 bits) 18 X 18 Bit Multiplier Blocks Block SelectRAM+ DCMs Maximum User I/O Pads Slices Max Distr RAM (Kb) 18 Kb Blocks Max Block RAM (Kb) XC2VP ,168 1, XC2VP ,768 3, XC2VP ,088 4, XC2VP ,880 9, , XC2VP ,816 13, , XC2VP40 0(2), 8, or ,632 19, , XC2VP50 0(2)or ,136 23, , XC2VP70 16 or ,448 33,088 1, , XC2VP100 0(2)or ,216 44,096 1, , ,164

P225/MAPLD 2004Pimentel31 Summary (nonlinear part only) Fclk max Time step # of gates # of FFPs usage Ex458 MHz0.17us160K5009% Ex555 MHz0.18 us370K130020% Ex660 MHz0.17 us500K170027% NOTE: 1) implemented on a Xilinx 2VP30 Virtex II PRO FPGA 2) results taken after placement and routing

P225/MAPLD 2004Pimentel32 Conclusion  Proposed a new approach to implement DRTPSSs based on programmable hardware and HDL languages  The proposed simulator produces results comparable to those obtained with the PSB/Matlab from Mathworks  The initial results show that the technique has the potential to create a breakthrough in DRTPSS and set a new level of performance for these simulation tools