Winter-Spring 2001Codesign of Embedded Systems1 Reactivity, Ports, and Signals in SystemC Part of HW/SW Codesign of Embedded Systems Course (CE )

Winter-Spring 2001Codesign of Embedded Systems2 Today programme Concept of Reactivity Reactivity facilities in SystemC Ports and Signals in SystemC Resolved Logic Vectors

Winter-Spring 2001Codesign of Embedded Systems3 Reactivity, Ports, and Signals in SystemC Reactivity Modeling in SystemC

Winter-Spring 2001Codesign of Embedded Systems4 Concept of Reactivity Property of Reaction to external events Inherent in HW => There MUST be some way to model it in any HDL Many SW or HW-SW systems are reactive as well: Any control systems (Chemical process control, ABS, …) Client-Server systems (Database Engines, …)

Winter-Spring 2001Codesign of Embedded Systems5 Concept of Reactivity (cont’d) Things to consider Events to react to Type of event (Clock edge, Signal change, some condition on signals or ports, …) Style of reaction Waiting style Suspend process until an event comes or some condition holds (i.e. Blocking wait) Watching style Do not suspend. But always WATCH if some condition holds. Then, react accordingly: e.g. Jump to a certain routine, or point of a routine. (Non-blocking wait)

Winter-Spring 2001Codesign of Embedded Systems6 Reactivity Facilities in SystemC Events to react to Sensitivity lists in SC_METHOD, SC_THREAD. And clock edge in SC_CTHREAD. Sensitivity to any event on a signal: sensitive data member of SC_MODULE Sensitivity to positive edge of a signal: sensitive_pos data member of SC_MODULE Sensitivity to negative edge of a signal: sensitive_neg data member of SC_MODULE Special case of infinite loop processes (SC_THREAD, SC_CTHREAD) Loop re-initialization, Wait for Signal condition

Winter-Spring 2001Codesign of Embedded Systems7 Reactivity Facilities in SystemC (cont’d) Style of reaction Waiting style wait() Both SC_THREAD and SC_CTHREAD wait_until( ) Only SC_CTHREAD Watching style Global watching: Always done. Cannot be disabled. Local watching: Done in certain parts of a process. Can be disabled and re-enabled (statically)

Winter-Spring 2001Codesign of Embedded Systems8 Global Watching Example SC_MODULE(data_gen) { sc_in_clk clk; sc_inout data; sc_in reset; void gen_data(); SC_CTOR(data_gen){ SC_CTHREAD(gen_data, clk.pos()); watching(reset.delayed()); } }; void gen_data() { if (reset == true) { data = 0; } while (true) { data = data + 1; wait(); data = data + 2; wait(); data = data + 4; wait(); } }

Winter-Spring 2001Codesign of Embedded Systems9 Global Watching in General void data_gen::gen_data () { // variable declarations // watching code if (reset == true) { data = 0; } // infinite loop while (true) { // Normal process function } }

Winter-Spring 2001Codesign of Embedded Systems10 Local Watching in General W_BEGIN // put the watching declarations here watching(...); watching(...); W_DO // This is where the process functionality goes... W_ESCAPE // This is where the handlers for the watched events // go if (..) { … } W_END

Winter-Spring 2001Codesign of Embedded Systems11 Local Watching Example void bus::xfer() { while (true) { // wait for a new address to // appear wait_until( newaddr.delayed() == true); // got a new address so //process it taddr = addr; datardy = false; // cannot accept new address // now data8 = taddr.range(7,0); start = true; // new addr // for memory controller wait(); // wait 1 clock between data // transfers data8 = taddr.range(15,8); start = false; wait(); data8 = taddr.range(23,16); wait(); data8 = taddr.range(31,24); wait(); // now wait for ready signal // from memory // controller wait_until(ready.delayed() == true); W_BEGIN watching(reset.delayed()); // Active value of reset // will trigger watching

Winter-Spring 2001Codesign of Embedded Systems12 Local Watching Example (cont’d) W_DO // the rest of this block is // as before // now transfer memory data // to databus tdata.range(7,0) = data8.read(); wait(); tdata.range(15,8) = data8.read(); wait(); tdata.range(23,16) = data8.read(); wait(); tdata.range(31,24) = data8.read(); data = tdata; datardy = true; // data is // ready, new addresses ok W_ESCAPE if (reset) { datardy = false; } W_END }

Winter-Spring 2001Codesign of Embedded Systems13 HW Design Using SystemC Ports and Signals

Winter-Spring 2001Codesign of Embedded Systems14 Ports and Signals Outline Port and Signal Usage Port Declaration Signal Declaration Valid Interconnections Special Objects: Clocks

Winter-Spring 2001Codesign of Embedded Systems15 Port and Signal Usage Port Module’s Interface to external world Signal Connect Modules’ ports together Convey values between ports (and hence modules) Module1Module2 Signal

Winter-Spring 2001Codesign of Embedded Systems16 Port Declaration Things to declare Port Mode Port Type Port Name Declaration Syntax Port_mode Port_name [, Port name, …];

Winter-Spring 2001Codesign of Embedded Systems17 Port Declaration Things to declare Port Mode Input: sc_in Output:sc_out Bi-directional(inout): sc_inout

Winter-Spring 2001Codesign of Embedded Systems18 Port Declaration Things to declare Port Mode Input: sc_in Output:sc_out Bi-directional(inout): sc_inout Port type C++ built-in type, SystemC types, and User defined types Scalar, and Array ports Special case: Resolved Logic Vector

Winter-Spring 2001Codesign of Embedded Systems19 Port Declaration Things to declare Port Mode and Type Input: sc_in Output:sc_out Bi-directional(inout): sc_inout Port Type C++ built-in type, SystemC types, and User defined types Scalar, and Array ports Special case: Resolved Logic Vector ‍Port Name Any valid C++ identifier

Winter-Spring 2001Codesign of Embedded Systems20 M1 sc_in i M1 sc_in i[10] Port Types Scalar Types C++ built-in types long, int, char, short, float, double SystemC types sc_int, sc_uint, sc_bigint, sc_biguint, sc_bit, sc_logic, sc_bv, sc_lv, sc_fixed, sc_ufixed, sc_fix, sc_ufix User defined types struct, class, typedef, enum Array types Declares an array of ports Each port must be individually bound, assigned, read, and written

Winter-Spring 2001Codesign of Embedded Systems21 Port Types (cont’d) Special case: Resolved Logic Vectors Usage Multi-driver ports (e.g. Buses) Resolution function: z and 0  0 z and 1  1 0 and 1  x x and (1 or 0 or x or z)  x Declaration syntax sc_in_rv port_name [, port_name, …]; sc_out_rv port_name [, port_name, …]; sc_inout_rv port_name [, port_name, …];

Winter-Spring 2001Codesign of Embedded Systems22 Signal Declaration Things to declare Signal type The same as port types Special case: Resolved vector signals Signal name Any valid C++ identifier Declaration syntax sc_signal sig_name [, sig_name, …];

Winter-Spring 2001Codesign of Embedded Systems23 Signal Types The same as port types Scalar Array Signals Special Case: Resolved Logic Vectors Declaration syntax sc_signal_rv sig_name [,sig_name, …];

Winter-Spring 2001Codesign of Embedded Systems24 Valid Interconnections M2M1 Higher-Level Module M1 Signals required Undocumented: Exceptions at least include: positional mapping Direct Connection No Signal required

Winter-Spring 2001Codesign of Embedded Systems25 Valid Interconnections (cont’d) Port reading and writing Reading a port = taking value of the signal bound to the port Writing a port = writing new value to the signal bound to the port, but AFTER the writing process has exited or been suspended Signal binding Each port to a single signal Repetitive bindings of a port  FIRST binding will remain effective

Winter-Spring 2001Codesign of Embedded Systems26 Special Objects: Clocks Clocks generate timing signals to synchronize simulation events No clock-signal is declared Instead, and sc_clock object is instantiated Declaration syntax sc_clock clk_name(“clk_name”, clk_period=1, clk_duty_cycle=0.5, first_edge_time=0, first_edge_type=true);

Winter-Spring 2001Codesign of Embedded Systems27 Special Objects: Clocks (cont’d) Multiple clocks are allowed Different frequencies Different phase relations Declaration point Typically generated at top-level module and passed down to lower-level modules The clock object or its signal (i.e. clock_object.signal() ) can be passed down SC_CTHREAD modules need the clock object itself sc_in_clk clk_object_name;

Winter-Spring 2001Codesign of Embedded Systems28 Special Objects: Clocks (cont’d) sc_clock clock("Clock", 20, 0.2, 3, false);

Winter-Spring 2001Codesign of Embedded Systems29 What we learned today Reactivity Concept SystemC facilities to model reactivity wait, wait_until global watching, local watching Ports, Signals, and Clocks in SystemC

Winter-Spring 2001Codesign of Embedded Systems30 Complementary notes: Assignments and Project Today is due date for Assignment 5 Take Assignment 6 Due date: Sat. Ordibehesht 15th Today is due date for Page-of-References of your project

Winter-Spring 2001Codesign of Embedded Systems31 Complementary notes: Extra classes “HW Synthesis Techniques Seminar” by S. Safari Date-Time: TODAY, 13 O’clock Place: Kwarizmi Hall, CE Dept.