1 A Novel Synthesis Algorithm for Reversible Circuits Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb Zamani {msaeedi, msedighi, aut.ac.ir Quantum Design Automation Lab, Computer Engineering Department Amirkabir University of Technology Tehran, Iran ICCAD 2007

2 Outline Introduction Basic Concept Previous Work Proposed Synthesis Algorithm Experimental Results Future Works Conclusions

3 Introduction Boolean reversible functions n-input, n-output, Unique output assignment Example: a 3-input, 3- output function (0,1,2,7,4,5,6,3) a0a0 a1a1 a2a2 f0f0 f1f1 f2f2 F AND

4 Power dissipation Landauer’s paper Every lost bit causes an energy loss When a computer erases a bit of information, the amount of energy dissipated into the environment is at least k B Tln2 Bennett’s paper To avoid power dissipation in a circuit, the circuit must be built with reversible gates

5 Applications of reversible circuits Low power CMOS design Reversible 4-bit adder “A reversible carry-look-ahead adder using control gates”, Integration, the VLSI Journal, vol. 33, pp , transistors with no power rails Optical computing Quantum computing Each unitary quantum gate is intrinsically reversible

6 Basic Concept Definition: A -CNOT is a (k+1)  (k+1) gate. It leaves the first k inputs unchanged, and inverts the last if and only if all others are 1. The unchanged lines are referred to as control lines. Clearly, the -CNOT gates are all reversible. The first three of these have special names. k inputs (k+1)th input

7 Basic Concept The zero-CNOT is just an inverter or NOT gate, and is denoted by N. It performs the operation (x)  (x  1) The one-CNOT, which performs the operation (y,x)  (y,x  y) is referred to as a Controlled- NOT, or CNOT (C). The two-CNOT is normally called a TOFFOLI (T) gate, and performs the operation (z,y,x)  (z,y,x  yz)

8 Basic Concept Reversible gate Various reversible gates CNOT-based gates NOT, CNOT, C 2 NOT (Toffoli), … Generalized Toffoli gate Positive controls Negative controls

9 Synthesis of Reversible Circuits High-level Description Gate-level circuits Physical Implementation Synthesis

10 Synthesis Algorithms Categories Constructive algorithms Construct a circuit from a given specification (i.e. truth table, PPRM expansion, decision diagrams, …) The resulted cost may not be optimized The time complexity of the algorithm may be too high

11 Synthesis Algorithms Categories (Cont’d) Search-based methods Also called substitution-based methods Use common sub-expressions to simplify the input function All possible gates should be evaluated at each step The best possible gates are selected based on a predefined function The algorithm convergence is not guaranteed An extensive exploration is required A time consuming procedure

12 Synthesis Algorithms Categories (Cont’d)

13 Synthesis Algorithms Categories (Cont’d) Transformation-based algorithms Used to improve the cost of circuit Sometimes applied on the results of other algorithms Usually use templates to optimize a circuit

14 Synthesis Algorithms Categories (Cont’d) A transformation based algorithm [18] Basic algorithm Uses row-based operations Output permutation Tries all n! output permutations to simplify the result Control input reduction To reduce the number of control qubits

15 Synthesis Algorithms Categories (Cont’d) Bidirectional algorithm To apply the method in both directions simultaneously Template matching A template consists of a sequence of gates to be matched and the sequence of gates to be substituted when a match is found A time consuming procedure

16 The Proposed Algorithm Definition: Output Translation The application of a reversible CNOT-based gate at the output side of a reversible specification F The result of using an output translation will also be reversible Only one function is changed at a time after using an output translation

17 The Goal of the Algorithm To generate a set of ordered output translations When applied to the reversible specification F, generates a i from f i g1g1 g2g2 gkgk a1a1 a2a2 anan f1f1 f2f2 fnfn

18 Applying an Output Translation Lemma 1 explains the results of using an output translation on a given specification: (a) Applying an output translation, exchanges the location of 2 k minterm pairs where k≤n-1 a0a0 a1a1 a2a2 f0f0 f1f1 f2f2 F

19 Exchanging Minterm Locations (b) Exchanging the location of 2 k-1 (k=n- m+1) minterm pairs produces the same result as applying an output translation if: All 2 k minterms have the same value on m-1 particular bit locations The two minterms of each pair differ only in one bit position

20 Exchanging Minterm Locations Proof: An output translation CNOT m (f 1,f 2,…,f m- 1,f m ) is applied to F where f k for k ∈ {1 to m-1} can also be a complemented function. This output translation maps f m to (f 1 f 2 …f m-1 ) ⊕ f m where the value of (f 1 f 2 …f m-1 ) is 1, there are 2 k (k=n-m+1) minterms. By using CNOT m, the location of these 2 k minterms are changed. Moreover, it can be checked CNOT m exchanges the locations of all 2 k- 1 minterm pairs m i : f m = 0 and m j : f m = 1.

21 Exchanging Minterm Locations Exchange location of minterm pair n-m m m-1 f1f1 f2f2 f3f3 f4f4 f5f5 f6f6 f7f7

22 Exchanging Minterm Locations Specification F(a 1,a 2,…,a n ) = (f 1,f 2,…f n ) Exchange location of minterm pair f1f1 f2f2 f3f3 f4f4 f5f5 f6f6 f7f a1a1 a2a2 a3a3 a4a4 a5a5 a6a6 a7a7 CNOT m (f 1,f 2,…,f m-1,f m )

23 The Proposed Algorithm Select the i th minterm of output functions Mark it as visited If its j th variable is not correct Find a minterm which differs from it in its j th variable If the new minterm is below the current minterm Exchange their locations Mark it as visited

24 The Proposed Algorithm (Cont’d) If the new minterm is above the current minterm If the new minterm is not in the right location Exchange their locations Mark it as visited Repeat the previous steps for all minterms and all variables until a k =f k for each k

25 The Proposed Algorithm Input: A reversible specification F (a1, a2, …, an) = (f1, f2, …, fn) Output: A set of reversible CNOT-based gates which when applied to F produces an identity function. Notation: The ith function (variable) of jth minterm is denoted as f i,mj (a i,mj ). Consequently, The ith minterm of jth function (variable) is denoted as m i,fj (m i,aj )

26 The Proposed Algorithm i = 1; repeat reset all of the 2n minterms to be unvisited. for each minterm m j (j = n) do if m j is not visited then if f i,mj ≠a i,mj then Extract the set of output translations (gates) based on Lemma 1 i = (i+1) mod n; until f i =a i for each i  (1…n)

27 The Proposed Algorithm begin mark the minterm m j,fi as a visited minterm select the minterm m k,fi which differs from m j,fi in its ith variable if m k,fi is below m j,f i then exchange the locations of m j,fi and m k,fi. (Therefore f i,mj =a i,mj ) mark the minterm m k,fi as a visited minterm else if m k,fi is above than m j,fi then if f p,mk ≠a p,mk (p=1...n) for at least one p then exchange the locations of m j,fi and m k,fi. (Therefore f i,mj =a i,mj ) mark the minterm m k,fi as a visited minterm end

28 Example a0a0 a1a1 a2a2 f0f0 f1f1 f2f2 f0f0 f1f1 f2f2 f0f0 f1f1 f2f2 f0f0 f1f1 f2f

29 Gate Extraction Method f 2 (new)=f 2  f 1 f f 3 (new)=f 3  f 1 f 2 ' f 2 (new)=f 2  f 1 f 3 a1a1 a2a2 a3a3 f1f1 f2f2 f3f3 Obtained gates should be applied in the reverse order

30 The Algorithm Convergence Theorem 1: The proposed algorithm will converge to a possible implementation after several steps Each output translation does not change the results of the previous ones Only one function is changed at a time after using an output translation

31 The Time Complexity Assumption: At most h gates are needed Search-based method n  2 n-1 gates must be evaluated to select the best possible gates at each step At most (n  2 n-1 ) h gates should be evaluated The proposed algorithm needs O(h×2 n ) steps to reach a result

32 Search-based Tree

33 Experimental Results Ckt #Specification Number of Gates Number of Searched Nodes ‎& Steps Proposed Algorithm (Basic) [15],[17] Proposed Algorithm (Basic) [17][15] 1(1,0,3,2,5,7,4,6) (7,0,1,2,3,4,5,6) (0,1,2,3,4,6,5,7) (0,1,2,4,3,5,6,7) (0,1,2,3,4,5,6,8,7,9,10,11,12,13,14,15) (1,2,3,4,5,6,7,0)332444

34 Experimental Results ( Cont’d ) Specification Number of GatesSearched Nodes Proposed Algorithm (Basic) [15], [17] Proposed Algorithm (Basic) [17][15] 7 (1,2,3,4,5,6,7,8,9,10,11,12,13,14, 15,0) (0,7,6,9,4,11,10,13,8,15,14,1,12,3,2,5) (3,6,2,5,7,1,0,4) (1,2,7,5,6,3,0,4) (4,3,0,2,7,5,6,1) (7,5,2,4,6,1,0,3) (6,2,14,13,3,11,10,7,0,5,8,1,15,12,4,9) Average

35 Experimental Results ( Cont’d ) Circuit #Specification Number of Gates Proposed Algorithm (Bidirectional) [18] (Bidirectional) 1(1,0,3,2,5,7,4,6)44 2(7,0,1,2,3,4,5,6)33 3(0,1,2,3,4,6,5,7)33 4(0,1,2,4,3,5,6,7)56 5(0,1,2,3,4,5,6,8,7,9, 10,11,12,13,14,15)714 6(1,2,3,4,5,6,7,0)33

36 Experimental Results ( Cont’d ) Specification Number of Gates Proposed Algorithm (Bidirectional) ‎[18] (Bidirectional) 7(1,2,3,4,5,6,7,8,9,10, 11,12,13,14,15,0)44 8(0,7,6,9,4,11,10,13, 8,15,14,1,12,3,2,5)44 9(3,6,2,5,7,1,0,4)67 10(1,2,7,5,6,3,0,4)67 11(4,3,0,2,7,5,6,1)57 12(7,5,2,4,6,1,0,3)59 13(6,2,14,13,3,11,10,7,0,5,8,1,15,12,4,9)917 Average

37 Experimental Results ( Cont’d ) All possible 3-input/3-output reversible circuits (8!=40320) are synthesized Average number of gates per circuit The proposed algorithm: 7.28 Average number of steps per circuit = It takes about 4 minutes to synthesize all circuits seconds for each circuit on average

38 Future Directions Working on the improvement of the resulting synthesized circuit By combining the proposed approach and the search-based methods By selecting the best possible variable at each step

39 Conclusions A new non-search based synthesis algorithm was proposed Several examples taken from the literature are used The proposed approach guarantees a result for any arbitrarily complex circuit It is much faster than the search-based ones

40 Thank you for your attention!