TDCPIX_2012

TDCPIX size Proposal numbering pads

TDCPIX_2012 Dimensions: x 20400µm² Thickness: 100µm

PROPOSAL NUMBERING PADS (1) We keep standard numbering

gnd_analog1_21vdd_serializer_0150gnd_digital1_299bandgap_dig_override148 vdd_analog1_22gnd_analog1_251vdd_digital1_2100gnd_temp149 gnd_digital1_23vdd_analog1_252gnd_analog1_2101vdd_temp150 vdd_digital1_24clk_dll_p53vdd_analog1_2102gnd_digital1_2151 gnd_tdc1_25clk_dll_n54gnd_analog1_2103vdd_digital1_2152 vdd_tdc1_26reset_coarse_frame_count_p55vdd_analog1_2104gnd_tdc1_2153 gnd_analog1_27reset_coarse_frame_count_n56gnd_digital1_2105vdd_tdc1_2154 vdd_analog1_28gnd_digital1_257vdd_digital1_2106gnd_tdc1_2155 mux_analog_out9vdd_digital1_258gnd_serializer_23107vdd_tdc1_2156 bandgap_ana_override10gnd_tdc1_259vdd_serializer_23108gnd_digital1_2157 multi_serial_out0_p 11vdd_tdc1_260gnd_serializer_23109vdd_digital1_2158 multi_serial_out0_n 12gnd_serializer_0161serial_out_p 110test_output_p 159 multi_serial_out0_p 13vdd_serializer_0162serial_out_n 111test_output_n 160 multi_serial_out0_n 14gnd_serializer_0163vdd_serializer_23112test_output_p 161 multi_serial_out0_p 15serial_out_p 64gnd_serializer_23113test_output_n 162 multi_serial_out0_n 16serial_out_n 65vdd_serializer_23114test_output_p 163 multi_serial_out0_p 17vdd_serializer_0166gnd_analog1_2115test_output_n 164 multi_serial_out0_n 18gnd_serializer_0167vdd_analog1_2116test_output_p 165 vdd_slvs19vdd_serializer_0168gnd_analog1_2117test_output_n 166 gnd_slvs20reset_global_p69vdd_analog1_2118vdd_digital1_2167 gnd_digital1_221reset_global_n70gnd_tdc1_2119gnd_digital1_2168 vdd_digital1_222test_pulse_in_p71vdd_tdc1_2120vdd_tdc1_2169 gnd_analog1_223test_pulse_in_n72mode_block_mux 121gnd_tdc1_2170 vdd_analog1_224serial_conf_in_p73mode_block_mux 122vdd_digital1_2171 gnd_analog1_225serial_conf_in_n74mode_block_mux 123gnd_digital1_2172 vdd_analog1_226gnd_pll75vdd_slvs124vdd_digital1_2173 multi_serial_out1_p 27vdd_pll76gnd_slvs125gnd_digital1_2174 multi_serial_out1_n 28gnd_pll77multi_serial_out2_p 126vdd_analog1_2175 multi_serial_out1_p 29vdd_pll78multi_serial_out2_n 127gnd_analog1_2176 multi_serial_out1_n 30clk_dig_p79multi_serial_out2_p 128vdd_analog1_2177 multi_serial_out1_p 31clk_dig_n80multi_serial_out2_n 129gnd_analog1_2178 multi_serial_out1_n 32clk_out_p81multi_serial_out2_p 130vdd_analog1_2179 multi_serial_out1_p 33clk_out_n82multi_serial_out2_n 131gnd_analog1_2180 multi_serial_out1_n 34serial_conf_out_p83multi_serial_out2_p 132vdd_analog1_2181 vdd_slvs35serial_conf_out_n84multi_serial_out2_n 133gnd_analog1_2182 gnd_slvs36vdd_slvs85gnd_digital1_2134vdd_digital1_2183 gnd_tdc1_237gnd_slvs86vdd_digital1_2135gnd_digital1_2184 vdd_tdc1_238gnd_analog1_287vdd_slvs136vdd_digital1_2185 gnd_analog1_239vdd_analog1_288gnd_slvs137gnd_digital1_2186 vdd_analog1_240gnd_serializer_2389multi_serial_out3_p 138vdd_tdc1_2187 gnd_analog1_241vdd_serializer_2390multi_serial_out3_n 139gnd_tdc1_2188 vdd_analog1_242gnd_serializer_2391multi_serial_out3_p 140test_output_p 189 gnd_serializer_0143serial_out_p 92multi_serial_out3_n 141test_output_n 190 vdd_serializer_0144serial_out_n 93multi_serial_out3_p 142test_output_p 191 gnd_serializer_0145vdd_serializer_2394multi_serial_out3_n 143test_output_n 192 serial_out_p 46gnd_serializer_2395multi_serial_out3_p 144test_output_p 193 serial_out_n 47vdd_serializer_2396multi_serial_out3_n 145test_output_n 194 vdd_serializer_0148gnd_tdc1_297temp_out146test_output_p 195 gnd_serializer_0149vdd_tdc1_298temp_adj147test_output_n 196

PROPOSAL NUMBERING PADS (2) We keep off all test_output pads out of the numbering

Pad size and definition

First pads row= 62 x µ Second row and test pads= 62 x 95.03µ

Pads definition Blue Pads: GND Pink pads: VDD (1.2V) Yellow pads: VDDA (1.2V) Green pads: signals

All serial_out pads are well surrounded with GND and VDD. CLK_DLL has reset_coarse_frame_count as neighbor. CLK_DIG has CLK_OUT as neighbor.

PN gnd Vdd vdd PN PN Vdd vdd P N Vdd gnd Actual Proposal

Bond wires length: GND: 0.7mm VDD= 1.4mm VDDA= 2.1mm Signals= 2.5mm First option: using rings for the power supplies And bond pads + micro vias for the signals. GND VDD VDDA

Bond wires length: GND: 0.7mm VDD, VDDA, Sig= 1.5mm Second row: 2.7 to 3.5mm Second option: using bond pads and micro vias for all connections

Wire Tail 25µ Foot 50µ Heel 25µ Min = 100µm Al wegde Wirebonding

High risk of shorting adjacent pads, extremely accurate bond placement required. Nice small probe mark, should have been at the end of pad but plenty of space for bond foot. Scratched through to the silicon in the uniform dark grey areas in center of the probe marks. Good bond pad design and especially PCB process control is essential.

Too short pad dimensions and thick passivation window can lead to weakened or broken heels. Passivation 5-7μm Reduced contact area and weakened heel (wire pushed over edge of pad). Accuracy of bond positioning: ±3µm silicon corner

Polyimide passivation not on each pad. It is preferable to create a region as shown in the picture in order to leave more space for the bonding

A 90° angle respect to the bonding pads 73µm pitch The possibility to probe the wafer before dicing The possibility to double the bond We would need bonding pads with 300µm length. Assuming