Uli Schäfer 1 JEM Status and plans Hardware -JEM1 -Status Firmware -Algorithms -Status Plans

Uli Schäfer 2 JEM1 16 x 6-channel de- serialisers : SCAN on 4 Input daughter modules w. XC2V1500. G-link / Opto daughter module Jet and Sum Processors XC2V2000 (BF package). Configuration : SystemACE 88 pair VMEVME each 165 pins FIO 60 80Mb/s TTCdec CAN System ACE 3 x Mb/s DES Input 2 B 1 A 0 V Input 5 E 4 D 3 C Input 8 H 7 G 6 F Input X 9 W DAQ/Timing/VME To JMM G G Jet R S T U Sum DAQ To SMM ROI Opto clock mirror

Uli Schäfer 3 JEM1 main board Components : Backplane and daughter connectors (TTC, input, G-link) Bus drivers (VME) and PECL line drivers/receivers Jet and Sum processors (BGA 1.28mm pitch) 2 CPLDs (VME / display) Front panel connectors/LEDs SystemACE configurator / flash chip CAN Voltage converters Production: One-stop Rohde & Schwarz Component procurement PCB production Adjustment of impedances Test protocols Assembly Visual inspection X-ray

Uli Schäfer 4 JEM1 H/W Status Input daughters: 8 PCBs made 1 assembled 3 to be assembled asap stand-alone test system set up by Andrey LVDS link tests successful BER 10e-14 (binary counter pattern w. f/w error detection Main board: 4 PCBs made assembly under way. Delayed due to component availability (voltage converters) G-link daughters: Design complete, PCB / assembly asap JTAG test adapters under design

Uli Schäfer 5 Algorithms (input / sum RTDP) Minor modifications (post RAL 11’03) to energy sum algorithm due to re-partitioning on JEM1. Receive energies 4η ×(8+3)φ × 2(e/h) : 88 channels total Synchronisation, parity, mask Generate jet elements E T =E e +E h (12 per input processor) Low threshold Saturate jet elements at 1 TeV and send to jet 80Mb/s, 5-bit wide From jet elements (E T ) calculate E X and E Y by multiplying cosφ, sinφ (accuracy: 10bit E T ×12-bit coefficient -> 12 bit,.25GeV resolution throughout) Threshold E T Pre-sum E X, E Y and E T, saturate at 4 TeV Send to sum 40Mb/s Final summation over 3 partial sums Quad-linear encoding of energies (8 bit, 4 TeV range, 1GeV resolution) Saturation (4TeV) Parity

Uli Schäfer 6 Firmware status For JEM1 some modifications were required, mainly in I/O stages (input synchronisation using DDR registers), block RAM, DLLs, hardware multipliers, clock mirror, FCAL handling, E X /E Y calculation on input processor, separate jet / sum processors, VME access. Change of channel count per input processor Complete re-write of the input processor. Coherent code for both JEM0 and JEM1  well debugged on JEM0. Partially tested on input module test adapter. Waiting for JEM1. New code for board control CPLD (VME) under way. Merging sum / ROC / control code will start soon.

Uli Schäfer 7 Plans JEM1 back from assembly next week (?) G-link daughter and further copies of input daughters available in April Production of (3) more main boards in May (1 week) Hope to have stable JEM1 f/w & s/w in ~1month Keep JEM0s up and running until a minimum of 2 JEM1s successfully operated.