Indium Phosphide Bipolar Integrated Circuits: 40 GHz and beyond Mark Rodwell University of California, Santa Barbara , fax ISSCC 2003 Special Topic Session: Circuits in Emerging Technologies, February 9, San Francisco

Applications of InP HBTs Optical Fiber Transceivers 40 Gb/s: InP and SiGe HBT both feasible ICs now available; market has vanished 80 & 160 Gb/s may come in time within feasibility for scaled InP HBT world may not need capacity for some time WDM might be better use of fiber bandwidth mmWave Transmission GHz, GHz, GHz Links Low atmospheric attenuation (weather permitting). High antenna gains (short wavelengths). 10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power GHz LANs: short range, wideband, broadcast Mixed-Signal ICs for Military Radar/Comms direct digital frequency synthesis, ADCs, DACs high resolution at very high bandwidths sought

Motivation for InP HBTs ParameterInP/InGaAsSi/SiGebenefit (simplified) collector electron velocity3E7 cm/s1E7 cm/slower  c, higher J base electron diffusivity40 cm 2 /s~2-4 cm 2 /slower  b base sheet resistivity 500 Ohm5000 Ohmlower R bb comparable breakdown fields Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation ~3:1 higher breakdown at a given bandwidth Problem for InP: SiGe has much better scaling & parasitic reduction Technology comparison today: Production SiGe and InP have comparable speed SiGe has much higher integration scales Production 1  m InP: low NRE, fast design cycle for SSI/MSI ICs to ~90 GHz (cost includes design time as well as $/mm 2 Present efforts in InP research community Development of low-parasitic, highly-scaled, high-yield fabrication processes

InP HBT fabrication processes today Mesa processes with self-aligned base contacts: Research labsModerately low yield → 1000 HBTs/IC 300 GHz f , 400 GHz f max, 7 V BVCEO, 100 GHz clock ~ 0.5  m emitter width Mesa processes with non-self-aligned base contacts: Production in GaAs HBT foundries (cell phone power amps) Somewhat better yield → 3000 HBTs/IC (?) 150 GHz f , 180 GHz f max, 7 V BVCEO, GHz clock 0.8  m emitter width, 1.0 $/mm 2 Exotic research processes for reduced C cb : 1) transferred-substrate, 2) strongly undercut collector mesa technology demonstrations, not IC technologies Present research processes in InP community: early development phases combine InP materials advantages with SiGe-like processes junction regrowth, dielectric sidewalls, trenches, pedestal implants… …more detail in later slides

Scaling key device parameterrequired change collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 0.707:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter resistance per unit emitter areadecrease 4:1 current densityincrease 4:1 base contact resistivity (if contacts lie above collector junction) decrease 4:1 base contact resistivity (if contacts do not lie above collector junction) unchanged Required transistor design changes required to double transistor bandwidth …easily derived by basic geometric calculations (C ’s,  ’s, I/C ’s all reduced 2:1)

Parasitic Reduction SiO 2 P base N+ subcollector N- thick extrinsic base : low resistance thin intrinsic base: low transit time wide emitter contact: low resistance narrow emitter junction: scaling (low R bb /A e ) wide base contacts: low resistance narrow collector junction: low capacitance At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics Much more fully developed in Si…

Optical Transmitters / Receivers are Mixed-Signal ICs TIA: small-signal LIA: often limiting MUX/CMU & DMUX/CDR: mostly digital Small-signal cutoff frequencies (f , f max ) are ~ predictive of analog speed Limiting and digital speed much more strongly determined by (I/C) ratios InP HBT has been well-optimized for f  & f max, less well for digital speed

How do we improve gate delay ?

Why isn't base+collector transit time so important ? Depletion capacitances present over full voltage swing, no large-signal reduction

Scaling Laws, Collector Current Density, C cb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse Collector capacitance charging time is reduced by thinning the collector while increasing current

Challenges with Scaling: Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length → sets minimum size for collector Solution: reduce base contact resistivity → narrower base contacts allowed Solution: decouple base & collector dimensions e.g. buried SiO 2 in junction (SiGe) Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements Current Density: self-heating, current-induced dopant migration, dark-line defect formation Loss of breakdown avalanche V br never less than collector bandgap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power Yield submicron InP processes have progressively decreasing yield

Technology Roadmaps for 40 / 80 / 160 Gb/s

InP-collector DHBTs: Self-Aligned Mesa Structure M Dahlstrom (UCSB/ONR), Amy Liu (IQE) 200 nm InP collector, 30 nm InGaAs base 8(10 19 ) /cm 3 base doping 1  m base contacts, 0.5  m x 7.5  m emitter junction 0.7  m emitter contact V ce =1.7 V J=3.7E5 A/cm 2 V br,ceo =7 V Collector / Emitter Ratio: 2.0 um / 0.5 um, 1.2 um / 0.5 um 0.7 um base contact width 0.3 um base contact width

Submicron InAlAs/InGaAs HBTs: High power gains at very high frequencies Gains are high at 220 GHz, but f max can’t be extrapolated UCSB/ONR: Miguel Urteaga transferred-substrate device 6-40, , GHz

f max = 460 GHz f t = 139 GHz InP-Collector Double Heterojunction Bipolar Transistors 0.5  m x 8  m emitter (mask) 0.4  m x 7.5  m emitter (junction) 1.0  m x 8.75  m collector 3000 Å collector drift region V BR,CEO = 8 J E =5*10 4 A/cm 2 UCSB/ONR: S. Lee transferred-substrate process

Large-Area (High Current) DHBTs for mm-Wave Power 8-finger device: 1 x 16  m emitter, 2 x 20  m collector UCSB/ARO: Y. Wei V BR,CBO > 7V Key challenges with high-current HBTs: - thermal stability (ballasting) - minimal base feed metal parasitic resistance - reliable electromagnetic models of feed networks

InP/InGaAs/InP Metamorphic DHBTs on GaAs substrates UCSB/ONR: Young-Min Kim Comparable performance to lattice-matched of similar design. Potential for SSI/MSI InP HBTs in cheap GaAs HBT foundry processes.

174 GHz, 6.3 dB, Single-Transistor Amplifier UCSB/ONR: Miguel Urteaga 0.3 um transferred-substrate HBT

Multi-Stage GHz Amplifiers Three-stage amplifier designs: 12.0 dB gain at 170 GHz 8.5 dB gain at 195 GHz Cascaded 50  stages with interstage blocking capacitors Cell Dimensions: 1.6 mm x 0.59 mm 0.3 um transferred-substrate HBT UCSB/ONR: Miguel Urteaga

75 GHz, 80 mW Power Amplifier 0.4  0.9 mm die, A E = 16 x (1  m x 16  m) = 256  m 2 transferred-substrate process Bias: I c =130 mA, V ce =4.5 V UCSB/ARO: Y. Wei mW is feasible; UCSB designs are constrained by yield difficulties with large # of fingers

87 GHz HBT static frequency divider InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO 200 GHz ft, 180 GHz fmax 2.5 x 10 5 A/cm 2 operation UCSB/ONR: PK Sundararajan

InPhi slides

OC-768 Linear Components Frequency (GHz) Transimpedance (dB ohms) (single-ended) Transimpedance Amplifier26 dB Limiting Amplifier 43 Gb/s Design Challenges: Gain flatness Peaking due to interconnect inductance, g m element phase shift, C cb variation, photodiode parasitics, single-ended / differential converter. Jaganathan & PullelaVetury, Pullela, Rodwelll curves with, without PIN parasitics -7.8 dBm BER ( ) PRBS

OC-768 Modulator Driver 30 dB gain, 40 GHz bandwidth, >10 dB S 11 & S 22 8 ps rise/fall (20-80%), ~0.9 ps RMS jitter 3 Vpp single ended output, 6 V differential Design Issues: Gain flatness Distributed line losses, current handling & loaded Z 0 Complexity of transmission-line layout Associated low-frequency droop Emitter follower negative resistance → peaking Efficacy of bypass capacitances Common-mode traveling-wave instability K. Krishnamurti et al

OC-768 Digital Components 4:1 Multiplexer / CMU 47 Gb/s 1:4 Demultiplexer / CDR (recovered 10 Gb/s data)

High current density 10 mA/  m 2 T-shaped polysilicon emitter 0.25  m junction wide contact low resistance, high yield Thin intrinsic base: low  b Thick extrinsic base: low R bb Low C cb collector junction collector pedestal CVD/CMP SiO 2 planarization regrown poly extrinsic base High-yield, planar processing high levels of integration LSI and VLSI capabilities SiGe clock rates up to 65 GHz Much more complex ICs than feasible in InP HBT InP HBT must reach higher integration scales or will cease to compete Very strong features of SiGe-bipolar transistors

Submicron InP HBT Development: Research Objective: speed extrinsic parasitic reduction deep submicron scaling Objective: yield planar process eliminate liftoff eliminate undercut etches Target Applications: High speed (>100 GHz) digital & mixed signal. 160 Gb/s optical fiber transmission Similar research efforts Rockwell/GCS/UCSB Vitesse. Lucent. TRW. HRL Labs. Double-poly (SiGe-like) HBT Planar HBT: Dielectric Sidewall Process

InP HBTs InP has better electron transport than SiGe → faster if comparable-quality fabrication processes are employed. Adaptation of 1-  m GaAs (cell phone) HBT foundry process to InP → Inexpensive, low NRE, low mask cost, fast design cycle Good process for SSI/MSI optical fiber and mm-wave ICs Not good for larger-scale digital / mixed-signal ICs Conventional but more highly scaled InP HBT processes → millimeter-wave power to 200 GHz, perhaps beyond. Future markets ? Present efforts in InP research community low-parasitic, highly-scaled, high-yield fabrication processes → 3:1 higher bandwidth at a given scaling generation → 3:1 higher breakdown at a given bandwidth Substantial risk of failure, substantial benefit if successful.