Unit 8 Combinational Circuit Design and Simulation Using Gates Fundamentals of Logic Design by Roth and Kinney.

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Presentation transcript:

Unit 8 Combinational Circuit Design and Simulation Using Gates Fundamentals of Logic Design by Roth and Kinney

8.1Review of Combinational Logic 1. Truth Table 2. K-maps 3. Multiple Gate Levels 4. Multiple Output Functions 5. NAND and NOR Circuits

8.2 Design of Circuits with Limited Gate Fan-In In practical logic design, the number of allowed inputs on each gate (fan-in) is limited. Factoring can be used to reduce the maximum number of gate inputs. See example, page Multiple Outputs—example page

8.3 Gate Delays and Timing Diagrams Switching is not instaneous—See figure Timing Diagram—Figure 8-5, Figure 8-6.

8.4 Hazards in Combinational Logic Unwanted switching transients can appear. Output should stay at 1, but could drop to 0 for a short period of time (static 1 hazard). Output should stay at 0, but could go to 1 for a short period of time (static 2 hazard) Dynamic Hazard—change 3 or more times See Figure 8.7.

8.5 Simulation and Testing of Logic Circuits Testing –Building the circuit. –Simulation of the circuit.

8.5 (cont.) Simulation is often used. –Verification that the design is logically correct. –Verification that the timing of the logic is correct. –Simulation of faulty components as an aid to finding tests for the circuit.

Design Problems Seven-Segment Display –Page 246 –Can be used to display 0-9. –Example: decimal “1” can be obtained by lighting segments 2 and 3 (see Figure 8-15)