Tom Newsom Vice President & General Manager SOC Business Unit May 2003 Agilent Technologies Accelerating the Future of DFT

CTL Press Event May 2003 Overview Increasing Market Momentum Agilent Introduces the FIRST Browser for DFT CTL: what is it, why it’s important Design-to-Test Process Agilent’s Power of DFT 3 Solution The Future…What’s Next?

CTL Press Event May 2003 Agilent Q2 Results Order Momentum (Feb.-April) Automated Test Group Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q Orders ($ Billion) Q1 03Q2 03 Orders Loss Revenue % of revenue % of revenue -$48 -$37 $136 $153 $115 $ $ Million 150

CTL Press Event May 2003 Introducing— SmarTest PG CTL Browser the FIRST browser for DFT CTL = Core Test Language (IEEE P1450.6)

CTL Press Event May 2003 MPEG 1394 ARM Core RAM EDA/design database Core ARM RAM MPEG 1394 Test development Turn-on & characterization Diagnostics MPEG 1394 ARM Core RAM Customer ship High-volume manufacturing SOC Development Process ‘Design for test’ (DFT) - general design procedures, practices and rules that allow cost-effective solutions to achieve SOC quality and fast time to market. Different colors = different tools from different companies.. interfering with DFT implementation.

CTL Press Event May 2003 MPEG 1394 ARM Core RAM EDA/design database Core ARM RAM MPEG 1394 Test development Turn-on & characterization Diagnostics MPEG 1394 ARM Core RAM Customer ship High-volume manufacturing SOC Development Process ‘Design for test’ (DFT) - general design procedures, practices and rules that allow cost-effective solutions to achieve SOC quality and fast time to market. Different colors = different tools from different companies... interfering with DFT implementation.

CTL Press Event May 2003 MPEG 1394 ARM Core RAM EDA/design database Core ARM RAM MPEG 1394 MPEG 1394 ARM Core RAM Test development Diagnostics Customer ship High-volume manufacturing SOC Development Process CTL allows the parts to talk with each other. Turn-on & characterization Different colors = different tools from different companies... interfering with DFT implementation.

CTL Press Event May 2003 MPEG 1394 ARM Core RAM EDA/design database Core ARM RAM MPEG 1394 MPEG 1394 ARM Core RAM Test development Diagnostics Customer ship High-volume manufacturing SOC Development Process CTL allows the parts to talk with each other. Turn-on & characterization Different colors = different tools from different companies... interfering with DFT implementation.

CTL Press Event May 2003 MPEG 1394 ARM Core RAM EDA/design database Core ARM RAM MPEG 1394 MPEG 1394 ARM Core RAM Test development Diagnostics Customer ship High-volume manufacturing SOC Development Process CTL allows the parts to talk with each other. Turn-on & characterization Different colors = different tools from different companies... interfering with DFT implementation.

CTL Press Event May 2003 The Answer— SmarTest PG CTL Browser

CTL Press Event May 2003 The Answer— SmarTest PG CTL Browser Finally, a user-friendly interface

CTL Press Event May 2003 The Evolution of DFT - an Analogy Internet Evolution Darpanet a set of tools and rules to allow geeks to communicate TCP/IP standards to move packets around HTML language of the Web HTML Browser allows humans to easily use the web DFT Evolution DFT a set of tools and rules to implement testability in an SOC P1500 embedded core test standard to add DFT to an SOC P CTL emerging as language for DFT SmarTest PG CTL Browser allows humans to implement DFT

CTL Press Event May 2003 The Power of the Browser Shift { C {si[1]=#; si[0]=#; so[0]=#; so[1]=#;} V { si_m123='d[0..4] si[1] si[0]'; so_m123='so[1] so[0] q[0..2]'; clk=P; WRCK=P; }} V { clk=0; WRCK=0; sc=0; CaptureWR=1; ShiftWR=0;} V { clk=P; WRCK=P;} V { CaptureWR=0; clk=0; WRCK=0;} } }ActiveState U; Pattern Pat1 { M do_intest { d[0..4]=00000; si[0]=111000; si[1]= ;} M do_intest { so[0]=001X11; so[1]=111100X1; q[0..2]=001; d[0..4]=01101; si[0]=011010; si[1]= ;} M do_intest { so[0]=1100X1; so[1]= ; q[0..2]=110; d[0..4]=11001; si[0]=110010; si[1]= ;} M do_intest { so[0]=010001; so[1]=1X110100; q[0..2]=00X; d[0..4]=01010; si[0]=001101; si[1]= ;} M do_intest { d[0..4]=00000; si[0]=111000; si[1]= ;} M do_intest { so[0]=001X11; so[1]=111100X1; q[0..2]=001; d[0..4]=01101; si[0]=011010; si[1]= ;} M do_intest { so[0]=1100X1; so[1]= ; q[0..2]=110; d[0..4]=11001; si[0]=110010; si[1]= ;} M do_intest { so[0]=010001; so[1]=1X110100; q[0..2]=00X; HTM L CTL

CTL Press Event May 2003 Without Champions Leading End-to-End Solution, Benefits from Standards Languish Lack of tools limited STIL Adoption STIL Adoption Agilent SmarTest PG STIL reader introduced Standard Published Standard Stable / Balloted

CTL Press Event May 2003 Customer Ship MPEG 1394 ARM Core RAM EDA/Design Database Core ARM RAM MPEG 1394 MPEG 1394 ARM Core RAM Test Development Turn-On & Characterization Diagnostics High-Volume Manufacturing S1 SmarTest PG CTL Browser Industry Leaders Speed End-to-End Solution for maximum benefit from CTL standard End-to-end tools speed CTL adoption CTL Adoption Standard stable Tools Delivered ARM1136JF-S™ core Program to prove concept DFT Compiler TetraMAX SoCBIST

CTL Press Event May 2003

CTL Press Event May EDA/Standards seamless design-to-test by driving partnerships and industry standards over 3100 hours invested by partners to ensure tools are interoperable “We’re doing it so our customers don’t have to.“ 2. Tools fast development and learning for the SOC development process Agilent SmarTest PG CTL browser 3. Agilent Single Scalable Platform with test processor per pin architecture Agilent’s Power of DFT 3 shortens TTM and lowers cost of test

CTL Press Event May EDA/Standards seamless design-to-test by driving partnerships and industry standards over 4500 hours invested by partners to ensure tools are interoperable “We’re doing it so our customers don’t have to.“ 2. Tools fast development and learning for the SOC development process Agilent SmarTest PG CTL browser 3. Agilent Single Scalable Platform with test processor per pin architecture Agilent’s Power of DFT 3 shortens TTM and lowers cost of test

CTL Press Event May EDA/Standards seamless design-to-test by driving partnerships and industry standards over 4500 hours invested by partners to ensure tools are interoperable “We’re doing it so our customers don’t have to.“ 2. Tools fast development and learning for the SOC development process Agilent SmarTest PG CTL browser 3. Agilent Single Scalable Platform with test processor per pin architecture Agilent’s Power of DFT 3 shortens TTM and lowers cost of test

CTL Press Event May EDA/Standards seamless design-to-test by driving partnerships and industry standards over 4500 hours invested by partners to ensure tools are interoperable “We’re doing it so our customers don’t have to.“ 2. Tools fast development and learning for the SOC development process Agilent SmarTest PG CTL browser 3. Agilent Single Scalable Platform with test processor per pin architecture Agilent’s Power of DFT 3 shortens TTM and lowers cost of test

CTL Press Event May 2003 FIRST ATE/EDA alliance for lower cost of test: Agilent/Synopsys FIRST ATE influenced design-to-test product: SmarTest PG FIRST Concurrent test design-to-test support: SmarTest PG FIRST ATE advocacy for P1450.3: Open standard for tester targeting paper FIRST Automatic scan compression design-to-test support: SmarTest PG FIRST ATE advocacy for open EDA databases: Synopsys MilkyWay FIRST Browser for CTL: SmarTest PG CTL Browser FIRST IEEE 1450/1999 STIL to ATE: SmarTest PG FIRST Support for SOC DFT diagnostics: Synopsys SoCBIST FIRST Industry Leaders Speed End-to-End CTL Solution: Agilent/Synopsys/STM/ARM FIRST Concurrent test paper and proposal: ITC Breaking Down the Wall Between Design and Test Power of DFT 3 - a history of FIRSTS

CTL Press Event May 2003 Power of DFT 3 shortens TTM and lowers cost of test 1. EDA/Standards Agilent will make CTL the language of DFT 2. Tools SmarTest PG CTL Browser See demo of complete SOC development process Semicon West Booth # Agilent Single Scalable Platform DFT solution available TODAY! New announcements & demo planned for Semicon West

CTL Press Event May 2003 Visit Agilent at Semicon West Booth # Talk to industry CTL experts Hear real customer stories Meet with Agilent IEEE committee members See LIVE demonstrations: Power of DFT 3 solution in process TODAY!! - meet w/Agilent partners and customers - see SOC DFT process demo at Semicon West SmarTest CTL Browser announced TODAY!! - see live demo at Semicon West Agilent DFT solution available TODAY !! - new announcements at Semicon West

CTL Press Event May 2003

CTL Press Event May 2003 Appendix

CTL Press Event May 2003 CTL Background IEEE P core test language (CTL) an extension to IEEE 1450 standard test interface language (STIL) utilizing IEEE P1500 embedded core test. IEEE P1500 standard for embedded core test (SECT) tells the IP core provider how to wrap cores in a standard way for testability all necessary information for test pattern re-use the need for test during SOC system integration structural and test modes information to allow insertion of IP cores in an SOC design

CTL Press Event May 2003 Example SOC pinout Agilent TPPA enables: Concurrent Test* SOC DFT sets up the cores for independent operation during test, allowing them to be executed concurrently using the TPPA. Can reduce test time typically by 30-50%. SoCBIST Diagnostics Synopsys’ SoCBIST is a SOC DFT technique that reduces the number of vectors by x and test time by over 10x. Diagnostics of failures detected by SoCBIST requires a TPPA enabled capability called “Selective BIST Capture.” BIST Control 1Gb Serial JTAG Scan Port800 MHz clock 50MHz clock Analog Instrument * Concurrent test requires an additional charge software license Agilent Test Processor Per Pin Architecture (TPPA) - what it means for SOC DFT