Embedded System Lab. Daeyeon Son Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories Yu Cai 1, Gulay Yalcin 2, Onur Mutlu 1, Erich F. Haratsch 4, Osman Unsal 2, Adrian Cristal 2,3, and Ken Mai 1 1 Carnegie Mellon University, 2 Barcelona Supercomputing Center, 3 Spain National Research Council, 4 LSI Corporation Daeyeon Son

Daeyeon Son Embedded System Lab. Introduction NAND flash memory is widely used in diverse applications, ranging from mobile electronics to enterprise servers. Unfortunately, as flash cells down to smaller technology nodes, they become increasingly vulnerable to circuit level noise, reducing the probability. In this paper, ‘NAC’ is proposed for correct error on flash cells by program interference. ‘NAC’ used the overall distribution and conditional distribution on the each state the logical values made by inserting electron into flash cells.

Daeyeon Son Embedded System Lab. Program Interference ‘Program Interference’ is occurred by word line and bit line on flash cells in block on SSDs. Unit of the page the flash cells is distinguished MSB, LSB page number for avoid the error as program interference. But, it can’t be perfect solution for modify the error by program interference.

Daeyeon Son Embedded System Lab. ‘ECC’ is not equal to ‘God’ ‘Error-Correcting Codes(ECC)’ is provided into SSD to protect the flash cells by occurring errors. But, ‘ECC’ has limited capacity and it can happens unexpected errors into flash cells. Fate of ‘ECC’ will be the ‘Titanic’ through a long time.

Daeyeon Son Embedded System Lab. Classification the threshold voltage SSDs can classify the threshold voltage on victim cell and neighbor cell using the survey about distribution on all flash cells. ‘Classification’ through reading the flash cells on the block can distinguish threshold voltage falls on different logical values. It can find the changing of threshold voltage state as not corrected by ‘ECC’ on each flash cells. Example of the ‘Classification’

Daeyeon Son Embedded System Lab. Neighbor-cell Assisted Error Correction ‘NAC’ is made for modify the threshold voltage on flash cell which occurred the error by voltage.

Daeyeon Son Embedded System Lab. Flash voltage distribution (4)

Daeyeon Son Embedded System Lab. Flash voltage distribution Shapes of the density in figure 2 are the ‘Gaussian Distribution’ as the ‘Standard Normal Distribution’. Falls of the threshold voltage distribution State of the floating gate

Daeyeon Son Embedded System Lab. Flash voltage distribution Authors’ statistical result shows like that: 1. It can calculate the optimum read reference voltage between two neighboring logical states. 2. ‘Raw Bit Error Rate’ can be minimized by factors that control the logical states. 3. Conditional distribution can modify the error as program interference higher than overall distribution. Sister ‘A’Sister ‘B’ “ Please don’t fight~ ”

Daeyeon Son Embedded System Lab. Optimizing the Read Reference Voltage (5) (6) (7)

Daeyeon Son Embedded System Lab. Optimizing the Read Reference Voltage (8) (9) Function of the standard normal distribution

Daeyeon Son Embedded System Lab. Optimizing the Read Reference Voltage (11) Center is average of data.

Daeyeon Son Embedded System Lab. Optimizing the Read Reference Voltage

Daeyeon Son Embedded System Lab. Minimizing Raw Error Bit Rate (12) (13, 14)

Daeyeon Son Embedded System Lab. SNR  ‘Overall’ vs ‘Conditional’ ‘SNR’ is difference the between normal distribution and target(noise) distribution. ‘Figure 2’, ‘Table 1’ show that should select the conditional(neighbor- cell) distribution better than overall(all in block) distribution.

Daeyeon Son Embedded System Lab. Minimizing BER using Conditional Distributions Optimum read reference voltage can divide the ‘Global’ and ‘Local’. ‘Global’ OPT is mean all distribution of the both neighbor aggressor cells and victim cell. ‘Local’ OPT is mean same logical state of the both neighbor aggressor cells and victim cell. (Probability of the each state will be got around ¼). Ref) Y. Cai et al., “Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling”, DATE 2013, pp. 2.

Daeyeon Son Embedded System Lab. Minimizing BER using Conditional Distributions In figure 5, ‘RBER’ for using exactly between aggressor cells and victim cell should be calculated by ‘Local’ optimum read reference voltage. Random value in each cells. Stable value in each cells.

Daeyeon Son Embedded System Lab. ‘NAR’ and ‘NAC’ ‘Neighbor-cell Assisted Reading(NAR)’ is enough to research about read reference voltage in all distributions. But, ‘NAR’ have much read latency on reading the information through program operation to flash cells. ‘Neighbor-cell Assisted Error Correction(NAC)’ presents simple solution for replace the ‘NAR’ to better on read latency. Step 1Step 2

Daeyeon Son Embedded System Lab. ‘NAC’ System ‘NAC Buffer’ into buffer of the SSD in figure 6 is used for store the current page and neighbor pages. ‘NAC Buffer’ can save the size of 5 pages. ‘NAC’ is implemented the micro-architecture into SSD.

Daeyeon Son Embedded System Lab. Prioritized ‘NAC’ In figure 9, the net number of corrected cells of type-N11 can reduce the total errors by 58%, 44% and 22% for flash memory at 3k, 10k and 30k P/E cycles. Prioritized ‘NAC’ can reduce as normal ‘NAC’ operation the various P/E cycles.

Daeyeon Son Embedded System Lab. Policy When Neighbor Cells Have Errors ‘Neighbor-Cells’ can also happen the error by program interference. But, its probability is very small and ‘ECC’ and ‘NAC’ system can cover the error case by program interference. Don’t worry~ It’s enough to correct the error.

Daeyeon Son Embedded System Lab. P/E Cycle Lifetime Evaluation ‘NAC fix N11+N01+N10+N00’ can increase lifetime about using normal value in range of logical values. The ECC design cost can be reduced by approximately 40% when NAC is employed. (22) Equation of the ECC failure rate

Daeyeon Son Embedded System Lab. Performance Evaluation ‘NAC’ is that a hit ratio of data is important because it uses the cache in SSD. As result, workloads that only have higher levels of spatial locality, of which there are fewer, can take advantage of the MSB neighbors.

Daeyeon Son Embedded System Lab. Performance Evaluation The read latency on ‘NAC’ can reduced by ‘NAC buffer’ for save correcting data about error flash cells. System with prefetching also can reduced the read latency. ‘NAC’ is efficient for reduce error and correcting latency.

Daeyeon Son Embedded System Lab. Conclusion Error related to program interference are very difficult to determine about variable for correcting into many word line and bit line. This paper have researched threshold voltage distribution in logical values and found efficient method to modify the voltage in flash cells. ‘Neighbor-Cell Assisted Error Correction’ method proposed the equation for optimized the read reference voltage. ‘NAC’ can reduce the read latency to modify the voltages.

Daeyeon Son Embedded System Lab. References 1. Y. Cai et al., “Error Patterns in MLC NAND Flash Memory: Measurement, Characterization and Analysis”, DATE Y. Cai et al., “Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation”, ICCD Y. Cai et al. “Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling”, DATE T. Kim et al., “Cell-to-cell Interference Compensation Schemes Using Reduced Symbol Pattern of Interfering Cells for MLC NAND Flash Memory”, IEEE Transactions on Magnetics Y. Cai et al. "FPGA-Based Solid-State Drive Prototyping Platform", FCCM 2011.