Instructor: Alexander Stoytchev CprE 281: Digital Logic

Registers & Counters CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

Administrative Stuff Homework 8 is out It is due on Monday Nov 11, 2013

Quick Review

A Parade of Flip-Flops

A simple memory element with NOT Gates x x x

A simple memory element with NAND Gates x x x

A simple memory element with NOR Gates x x x

Basic Latch

A simple memory element with NOR Gates

ResetSet

Reset SetQ [ Figure 5.3 from the textbook ] A memory element with NOR gates

[ Figure 5.3 & 5.4 from the textbook ] Two Different Ways to Draw the Same Circuit

Gated SR Latch

[ Figure 5.5a from the textbook ] Circuit Diagram for the Gated SR Latch

This is the “gate” of the gated latch

Circuit Diagram for the Gated SR Latch Notice that these are complements of each other

S R Clk Q Q [ Figure 5.6 from the textbook ] Gated SR latch with NAND gates

S R Clk Q Q Gated SR latch with NAND gates In this case the “gate” is constructed using NAND gates! Not AND gates.

Gated D Latch

[ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch

Edge-Triggered D Flip-Flops

(a) Circuit D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk [ Figure 5.9a from the textbook ] Master-Slave D Flip-Flop

D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk

T Flip-Flop

[ Figure 5.15a from the textbook ] T Flip-Flop

[ Figure 5.15a from the textbook ] T Flip-Flop Positive-edge-triggered D Flip-Flop

[ Figure 5.15a from the textbook ] T Flip-Flop What is this?

Q Q T D

Q Q T D += ?

T 0 1 D Q Q Clock T Flip-Flop

What is this? += ?

T D Q Q Clock T Flip-Flop

JK Flip-Flop

[ Figure 5.16a from the textbook ] JK Flip-Flop D = JQ + KQ

[ Figure 5.16 from the textbook ] JK Flip-Flop JQ Q K 0 1 Qt1+  Qt  0 (b) Truth table(c) Graphical symbol J Qt  1 K D Q Q Q Q J Clock (a) Circuit K

JK Flip-Flop (How it Works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K=1 then it behaves as a T flip-flop

Registers

Register (Definition) An n-bit structure consisting of flip-flops

A simple shift register [ Figure 5.17 from the textbook ]

Parallel-access shift register [ Figure 5.18 from the textbook ]

Counters

A three-bit up-counter [ Figure 5.19 from the textbook ]

A three-bit up-counter [ Figure 5.19 from the textbook ] T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count (b) Timing diagram

A three-bit down-counter [ Figure 5.20 from the textbook ]

A three-bit down-counter [ Figure 5.20 from the textbook ] T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count (b) Timing diagram

Synchronous Counters

A four-bit synchronous up-counter [ Figure 5.21 from the textbook ]

A four-bit synchronous up-counter [ Figure 5.21 from the textbook ]

Derivation of the synchronous up-counter [ Table 5.1 from the textbook ] Clock cycle 0080 Q 2 Q 1 Q 0 Q 1 changes Q 2

A four-bit synchronous up-counter [ Figure 5.21 from the textbook ]

Inclusion of Enable and Clear capability [ Figure 5.22 from the textbook ] T Q Q Clock T Q Q Enable Clear_n T Q Q T Q Q

Questions?

THE END