Announcements Assignment 8 posted –Due Friday Dec 2 nd. A bit longer than others. Project progress? Dates –Thursday 12/1 review lecture –Tuesday 12/6 project demonstrations in the lab (no presentations) –Sunday 12/11 project reports due to me by –Tuesday 12/13 final exam, 1pm-3pm here.

Lecture 23 Overview More Sequential Logic –Ant Brain Example –State Minimization –Mealy/Moore Machines

Example: Ant Brain ( Ward, MIT ) Sensors: L and R antennae, 1 if in touching wall Actuators: F - forward step, TL/TR - turn left/right slightly Goal: find way out of maze Strategy: Wall follower: keep the wall on the right: walk through the maze, tapping the wall with the right antenna. start end

Ant Brain: Defining the states We need to turn the strategy into an algorithm - define a series of states and the appropriate response to them. Special case I : Left antenna touching the wall Turn 180 degrees - turn left until right antenna no longer touches the wall.

Ant Brain: Defining the states Special case II : No antenna touching the wall Ant lost - go straight forward

A: Following wall, touching Go forward, turning left slightly B: Following wall, not touching Go forward, turning right slightly C: Break in wall Go forward, turning right slightly D: Hit wall again Back to state A State D is the same as state A E: Wall in front Turn left until... F:...we are here, same as state B State F is the same as State B G: Turn left until... State G is effectively the same as State E LOST: Forward until we touch something Ant Brain Complete instruction set: describes the instructions required for the ant to walk through the maze, tapping the wall with its right antenna

Designing an Ant Brain Draw the State Diagram Transition arrows represent input from antennae Actuators F=forward step, TL=turn left slightly, TR=turn right slightly R’R’ C (TR, F) R’R’ L’ R’ B (TR, F) L’ R’ L R A (TL, F) R L’ R L + R E/G (TL) L + R LOST (F) L’ R’

Synthesizing the Ant Brain Circuit Encode States Using a Set of State Variables The encoding is an arbitrary choice - may affect cost, speed Use Transition Truth Table Define next state function for each state variable Define output function for each output Implement next state and output functions using combinational logic

Transition Truth Table First, using symbolic states and outputs, derive the transition truth table LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’R’ R’R’ L’ R’ R L R L’ R L + R L’ R’ stateLRnext state current outputs LOST00LOSTF LOST–1E/GF LOST1– E/GF A00BTL, F A01ATL, F A1– E/GTL, F B– 0CTR, F B– 1ATR, F

stateLRnext stateoutputs X,Y,ZX', Y', Z'FTRTL LOST- 000 E/G- 001 A- 010 B- 011 C- 100 it now remains to "synthesize" these 6 functions: to design output logic and next state logic to produce this result Synthesis 5 states : 3 state variables required (X, Y, Z) State assignment: Convert symbolic states to bits (in this case, arbitrarily chosen) Also represent outputs with bits An alternative Assignment: LOST- 000 E/G- 101 A- 110 B- 111 C- 100

stateinputsnext stateoutputs X,Y,ZL RX +,Y +,Z + FTRTL solve (using K-maps) for each output and next state e.g. TR = X + Y Z X + = X R’ + Y Z R’ = R’ TR Synthesis of Next State and Output Functions e.g.: Unused states 101, 110 & 111 are missing Assumed don't cares 3 state bits + 2 inputs means 2 5 = 32 rows in the transition table. Here we only show those we care about.

Circuit Implementation Outputs are a function of the current state only Moore machine LRLR F TR TL Next State Current State output logic next state logic X+X+ Y+Y+ Z+Z+ XYZ stateinputsnext stateoutputs X,Y,ZL RX +,Y +,Z + FTRTL

Ant is in deep trouble if it gets in this state Don’t Cares in FSM Synthesis What happens to the "unused" states (101, 110, 111)? They can be exploited as don't cares to minimize the logic If these states can't happen, then we don't care what the functions do if these states do happen, we may be in trouble 000 (F) 001 (TL) 010 (TL, F) 011 (TR, F) 100 (TR, F) R’R’ R’R’ L’ R’ R L R L’ R L + R L’ R’

State Minimization Fewer states may mean fewer state variables High-level synthesis may generate many redundant states Two states are formally equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same Two conditions for two states to be equivalent: 1)Output must be the same in both states (The nodes in the state diagram must be the same) 2) Must transition to equivalent states for all input combinations (The arrows FROM the nodes in the state diagram must result in the same state)

Ant Brain Revisited Two conditions for two states to be equivalent: 1)Output must be the same in both states (The nodes in the state diagram must be the same) 2) Must transition to equivalent states for all input combinations (The arrows FROM the nodes in the state diagram must result in the same state) Any more equivalent states? LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’R’ R’R’ L’ R’ R L R L’ R L + R L’ R’

New Improved Brain Merge equivalent B and C states Behavior is exactly the same as the 5-state brain We now need only 2 state variables rather than 3 LOST (F) E/G (TL) A (TL, F) B/C (TR, F) R’R’ L’ R’ R L L’ R L + R L’ R’

New Improved Brain LOST (F) E/G (TL) A (TL, F) B/C (TR, F) R’R’ L’ R’ R L L’ R L + R L’ R’ Only 2 state variables:

stateinputs next stateoutputs X,YL RX +,Y + FTRTL New Brain Implementation X F Y R L X TR Y R L X TL Y R L X X+ Y R L X Y+ Y R L Karnaugh Maps: Use these to derive combinational logic for outputs (only depends on X & Y) Use these to derive combinational logic for next state

react right away to leaving the wall Mealy vs. Moore Machines Moore: outputs depend on current state only Mealy: outputs depend on current state and inputs Ant brain is a Moore Machine Internal state defines the outputs Output does not react immediately to input change We could have specified a Mealy Machine Outputs have immediate reaction to inputs As inputs change, so does next state, doesn’t commit until clocking event A L’ R’ / TR, F L / TL L’ R / TL, F

D/1 E/1 B/0 A/0 C/ reset currentnext resetinputstatestateoutput 00AB0 01AC0 00BB0 01BD0 00CE0 01CC0 00DE1 01DC1 00EB1 01ED1 Specifying Outputs for a Moore Machine Output is only function of state Specify output in state bubble in state diagram Example: sequence detector for 01 or 10

currentnext resetinputstatestateoutput 1––A0 00AB0 01AC0 00BB0 01BC1 00CB1 01CC0 B A C 0/1 0/0 1/1 1/0 reset/0 Specifying Outputs for a Mealy Machine Output is function of state and inputs Specify output on transition arc between states Example: sequence detector for 01 or 10

state feedback inputs outputsreg Combinational logic for Next State Logic for outputs inputsoutputs state feedback reg Combinational logic for Next State Logic for outputs Comparison of Mealy and Moore Machines Mealy Machines tend to have less states Different outputs on arcs rather than additional states Moore Machines are safer to use Outputs change only at clock edge (always one cycle later) In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback Mealy Machines react faster to inputs React in same cycle – don't need to wait for clock In Moore machines, must wait for clock, and more logic may be necessary to decode state into outputs – more gate delays after state elements. Moore Mealy

Mealy and Moore Examples Recognize A,B = 0,1 Mealy or Moore?

Mealy and Moore Examples Recognize A,B = 0,1 Mealy or Moore? Moore Neither has a connection between the inputs and the output logic. Both are Moore machines.

Mealy and Moore Examples (cont’d) Recognize A,B = 1,0 then 0,1 Mealy or Moore?

Mealy and Moore Examples (cont’d) Recognize A,B = 1,0 then 0,1 Mealy or Moore? Mealy Synchronous Mealy Direct connection between inputs and output logic, but the inputs can only change on the clocking event