Timing Distribution System (TDS) 9 April, 2010 Greg Deuerling Rick Kwarciany Neal Wilcer.

Slides:



Advertisements
Similar presentations
Status of the CTP O.Villalobos Baillie University of Birmingham April 23rd 2009.
Advertisements

01/11/2002SNS Software Final Design Review1 V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls.
 WAN uses Serial ports  Ethernet Ports:  Straight through  Cross over.
SciFi Tracker DAQ M. Yoshida (Osaka Univ.) MICE meeting at LBNL 10.Feb.2005 DAQ system for KEK test beam Hardware Software Processes Architecture SciFi.
M. Kreider, T. Fleck WhiteRabbit 1 WhiteRabbit Timing System.
Dirk Zimoch, EPICS Collaboration Meeting, Vancouver 2009 Real-Time Data Transfer using the Timing System (Original slides and driver code by Babak Kalantari)
Dale E. Gary Professor, Physics, Center for Solar-Terrestrial Research New Jersey Institute of Technology 1 11/7/2011OVSA Technical Design Meeting.
Alice EMCAL Meeting, July 2nd EMCAL global trigger status: STU design progress Olivier BOURRION LPSC, Grenoble.
1 Fall 2005 Extending LANs Qutaibah Malluhi CSE Department Qatar University Repeaters, Hubs, Bridges, Fiber Modems, and Switches.
TCSS 372A Computer Architecture. Getting Started Get acquainted (take pictures) Discuss purpose, scope, and expectations of the course Discuss personal.
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
Ionization Profile Monitor Project Current Status of IPM Buffer Board Project 10 February 2006 Rick Kwarciany.
Intel ® Research mote Ralph Kling Intel Corporation Research Santa Clara, CA.
CSS Lecture 2 Chapter 3 – Connecting Computer Components with Buses Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level, Tri-state,
Sept EE24C Digital Electronics Project Design of a Digital Alarm Clock.
Lecture 12 Today’s topics –CPU basics Registers ALU Control Unit –The bus –Clocks –Input/output subsystem 1.
Bill W. Haynes Slide 1 February 26, 2002 CKM Precision Timing CKM Workshop In San Luis Potosi, Mexico u Common Design for Multiple Timing Applications.
1 Version 3.1 Module 4 Learning About Other Devices.
3/7/05A. Semenov Batch-by-Batch Intensity Monitor 1 Two-Channel Batch by Batch Intensity Monitor for Main Injector BBI.
8254 Programmable Interval Timer
TID and TS J. William Gu Data Acquisition 1.Trigger distribution scheme 2.TID development 3.TID in test setup 4.TS development.
Leo Greiner IPHC testing Sensor and infrastructure testing at LBL. Capabilities and Plan.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
Low Cost Radar and Sonar using Open Source Hardware and Software
AT91 Embedded Peripherals
Tuesday September Cambridge1 GDCC “next replacement of the LDA” Franck GASTALDI.
SNS Integrated Control System SNS Timing Master LA-UR Eric Bjorklund.
U N C L A S S I F I E D FVTX Detector Readout Concept S. Butsyk For LANL P-25 group.
PHENIX upgrade DAQ Status/ HBD FEM experience (so far) The thoughts on the PHENIX DAQ upgrade –Slow download HBD test experience so far –GTM –FEM readout.
Status of the NO ν A Near Detector Prototype Timothy Kutnink Iowa State University For the NOvA Collaboration.
June 3, 2005H Themann SUSB Physics & Astronomy 1 Phenix Silicon Pixel FEM S. Abeytunge C. Pancake E. Shafto H. Themann.
CSS 372 Oct 4th - Lecture 3 Chapter 3 – Connecting Computer Components with Buses Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level,
21-Aug-06DoE Site Review / Harvard(1) Front End Electronics for the NOvA Neutrino Detector John Oliver Long baseline neutrino experiment Fermilab (Chicago)
1 MICE Tracker Readout Update, Preparation for Cosmic Ray Tests Cosmic Ray Tests at RAL AFE-IIt Firmware Development VLSB Firmware Development Summary.
SNS Integrated Control System Timing Clients at SNS DH Thompson Epics Spring 2003.
C. Combaret DIF_GDIF_MDIF_D ASU 6x 24 HR2 ASU USB Hub RPi USB2 DCC SDCC RPi USB 1 hub+Rpi for 4 cassettes 1 DCC for 8 cassettes (1 spare) Trigger.
Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.
Xiangming Sun1PXL Sensor and RDO review – 06/23/2010 STAR XIANGMING SUN LAWRENCE BERKELEY NATIONAL LAB Firmware and Software Architecture for PIXEL L.
The Main Injector Beam Position Monitor Front-End Software Luciano Piccoli, Stephen Foulkes, Margaret Votava and Charles Briegel Fermi National Accelerator.
Timing Requirements for Spallation Neutron Sources Timing system clock synchronized to the storage ring’s revolution frequency. –LANSCE: MHz.
ATLU for AIDA High Rate Synchronous as well as Asynchronous 21/11/2013David Cussans, AIDA WP9.3, DESY1.
FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)
January 31, MICE DAQ MICE and ISIS Introduction MICE Detector Front End Electronics Software and MICE DAQ Architecture MICE Triggers Status and Schedule.
12GeV Trigger Workshop Christopher Newport University 8 July 2009 R. Chris Cuevas Welcome! Workshop goals: 1.Review  Trigger requirements  Present hardware.
1 07/10/07 Forward Vertex Detector Technical Design – Electronics DAQ Readout electronics split into two parts – Near the detector (ROC) – Compresses and.
28 June 2004ATLAS Pixel/SCT TIM FDR/PRR1 TIM tests with ROD Crate John Hill.
REDNet - Status overview Rok Stefanic Ziga Kroflic
Fermilab February 17, 2003Recycler BPM Front-end1 Duane C. Voy
Mathias Reinecke CALICE week Manchester DIF development – Status and Common Approach Mathias Reinecke for the CALICE DAQ and Front-End developers.
Time and amplitude calibration of the Baikal-GVD neutrino telescope Vladimir Aynutdinov, Bair Shaybonov for Baikal collaboration S Vladimir Aynutdinov,
Integration and commissioning of the Pile-Up VETO.
Precise measurement of physical link delay 802.1as, IEEE 802 plenary Lu Huang
PSD upgrade: concept and plans - Why the PSD upgrade is necessary? - Concept of the PSD temperature stabilization and control - Upgrade of HV control system.
ATLU for AIDA High Rate Synchronous as well as Asynchronous 21/11/2013 David Cussans, AIDA WP9.3, DESY 1.
15-Aug-08DoE Site Review / Harvard(1) Front End Electronics for the NOvA Neutrino Detector John Oliver, Nathan Felt, Sarah Harder Long baseline neutrino.
1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.
Sumary of the LKr WG R. Fantechi 31/8/2012. SLM readout restart First goal – Test the same configuration as in 2010 (rack TS) – All old power supplies.
PC-based L0TP Status Report “on behalf of the Ferrara L0TP Group” Ilaria Neri University of Ferrara and INFN - Italy Ferrara, September 02, 2014.
The Data Handling Hybrid Igor Konorov TUM Physics Department E18.
Event Display The DAQ system architecture The NOA Data Acquisition system with the full 14 kt far detector P.F. Ding, D. Kalra, A. Norman and J. Tripathi.
NO A Data Acquisition System TIPP 2011 Sue Kasahara, University of MN for the NO A DAQ Group: K. Biery, G. Deuerling, N. Felt, A. Gavrilenko, S. Goadhouse,
April 2006 CD1 Review NOvA DAQ 642, hits/sec avg. 20,088 Front-End Boards (~ 3 MByte/sec data rate per FEB) 324 Data Combiner Modules,
Using VDSL2 over Copper in the Vertical String
DIF – LDA Command Interface
ABC130: DAQ Hardware Status Matt Warren et al. Valencia 3 Feb 2014
AHCAL Beam Interface (BIF)
SLC-Aware IOC LCLS Collaboration Jan 26, 2005
ECAL Integration / CALICE DAQ task force
Sheng-Li Liu, James Pinfold. University of Alberta
Readout Systems Update
Presentation transcript:

Timing Distribution System (TDS) 9 April, 2010 Greg Deuerling Rick Kwarciany Neal Wilcer

NOvA Timing Distribution System Features Distributes system clock and synchronizes time stamp registers of all DAQ devices on detector. All timing system links are CAT5e cables except Near Detector MTDU to STDU1 (need fiber to go the 200 or so meters). Configurable and monitorable via DCS. DCMs have two clock system interfaces, so a complete redundant clock system can be deployed if desired. Can correct for cable delays using TOF/2 method if desired. April 2010 Collaboration Meeting

TDS to DAQ System GPS TDU MTDU STDU April 2010 Collaboration Meeting

Master Timing Unit April 2010 Collaboration Meeting

Slave Timing Unit April 2010 Collaboration Meeting

Some Functional Details Timing system’s main connection to DCS is to MTDU via Ethernet. Timing critical commands are transmitted to system from MTDU through timing links. Timing critical events are synchronized with SYNC signal on timing links (generated by MTDU). STDU can be queried for status via Ethernet, but cannot inject commands or SYNCs. MTDU and STDU firmware remotely loadable via Ethernet. April 2010 Collaboration Meeting

On System Startup… MTDU put into “Delay Learn” mode. –Transmits a SYNC pulse to slaves. –Measures time of round trip via ECHO signal. –All STDUs and DCMs do the same. MTDU synchronizes timing registers in all DAQ devices. –Transmits Timing Register Preset command. –Issues SYNC to start Timing Counter on all devices on the same clock cycle. MTDU issues command(s) to set mode in all DCMs and FEBs. –FEB and DCM control registers write accessible via timing link. MTDU periodically issues a Timing Register Verify command as a sanity check. April 2010 Collaboration Meeting

MTDU April 2010 Collaboration Meeting

GPS Module April 2010 Collaboration Meeting

TOF/2 (Time of Flight / 2) April 2010 Collaboration Meeting

Schedule & Summary We have two assembled prototype TDU modules (STDU and MTDU use same board). Hardware is working. We have four GPS units and four antennas. We expect to have two assembled CPU daughter boards and two more TDU modules by end of month. For NDOS we will need: –One Master Timing unit. –One CPU daughter board. –One GPS module and antenna. –1 Slave Timing Distribution unit (two would be nice). We expect to have firmware working that will be functional but may not be 100% feature complete. April 2010 Collaboration Meeting

Timing Distribution System (TDS) Questions? April 2010 Collaboration Meeting

Supporting Notes Following are notes of the above slides July 21-23, 2009 Director's CD-3b Review

Master Timer Incorporates a common view GPS trained clock generator with a time- stamp counter. Capable of decoding Fermilab beam timing signals (RF-Clk, BSync, TClk, MDat). Capable of broadcasting time-of-day and time-stamp to Far Detector (100Mb ethernet). Provides a USB slave port (alternate computer connection). Provides repetitive timing & control packets to downstream distribution boxes. Measures & stores roundtrip time-of-flight of timing commands. July 21-23, 2009 Director's CD-3b Review

Timing Distribution Unit Coherent timing along the backbone of the detector. –Timing is referenced to the far-end cable loopback. –Synchronization is within +/- 1/2 clock cycle (16.834Mhz). Synchronization is based on the roundtrip time-of-flight of timing packets. –Digital equivalent of the time-of-flight of a reflection on a coax cable using a Time Domain Reflectometer. –Time-of-flight measurements are stored for later readout. Propagation delays are self compensated –No need to match cable pair lengths (xmt & rcv) Distributes Clock, Timing & Control commands to DCMs July 21-23, 2009 Director's CD-3b Review

Timing Distribution System (old design) 0013XX 0012XX0009XX0002XX0001XX July 21-23, 2009 Director's CD-3b Review