ABC: A System for Sequential Synthesis and Verification BVSRC Berkeley Verification and Synthesis Research Center Robert Brayton, Niklas Een, Alan Mishchenko, Jiang Long, Sayak Ray, Baruch Sterin UC Berkeley Thanks to NSF, SRC, and industrial sponsors: Intel, IBM, Synopsys, Magma, Actel, Altera, Atrenta, Intrinsity, Jasper, Tabula, Verific, Real Intent, Oasys

ABC in a Design Flow System Specification RTL Logic synthesis Technology mapping Physical synthesis Manufacturing ABC Verification

Design size, gate count Time, years Conjunctive normal forms Truth tables Sum-of- products Binary Decision Diagrams Historical Perspective And-Inverter Graphs ,000,000 Espresso, MIS, SIS SIS, VIS, MVSIS ABC ,000

Areas Addressed by ABC Combinational synthesisCombinational synthesis –logic optimization –technology mapping –resynthesis after mapping Sequential synthesisSequential synthesis –retiming –structural register sweep –merging sequential equivs Formal verificationFormal verification –combinational equivalence checking (CEC) –bounded sequential verification (BMC) –unbounded sequential verification –verification using synthesis history

Combinational Synthesis with Structural Choices Traditional synthesis D2 D1 Synthesis with choices D3 HAIG D2 D1 D3D4 D4 Perform synthesis and keep track of changesPerform synthesis and keep track of changes –Iterate fast local AIG rewriting with a global view (via hash table) –Collect AIG snapshots and prove equivalences across them –Use equivalences (choices) during technology mapping ObservationsObservations –Leads to improved QoR after technology mapping –Successfully applied to designs with 1M+ gates

Technology Mapping Customizable structural mapping with priority cutsCustomizable structural mapping with priority cuts –Computes a small subset of cuts without impacting the QoR –Uses structural choices ObservationsObservations –Controls QoR tradeoffs –Minimizes delay/area, wire count, switching activity, etc –Successfully applied to 1M gate designs a b cd f e Primary inputs Primary outputs Choice node AIG Mapped network  a b c d e f LUT

Minimum-Perturbation Retiming Reduces delay after retiming, while minimizing the number of flops movedReduces delay after retiming, while minimizing the number of flops moved –Produces a trade-off: delay gain vs. the number of flops moved –Handles “industrial stuff” and retimes over white boxes! –Computes new initial state after backward retiming Allows the user to control the resourcesAllows the user to control the resources –Desired delay gain –Maximum allowed number of flops moved –Maximum area increase after retiming ObservationsObservations –Can be useful before and after placement –Can be implemented efficiently Runs in less than a minute for 1M gatesRuns in less than a minute for 1M gates Delay Flops moved

Sequential Verification Property checkingProperty checking –Takes design and property and makes a miter (AIG) Equivalence checkingEquivalence checking –Takes two designs and makes a miter (AIG) The goal is to transform AIG until the output can be proved const 0The goal is to transform AIG until the output can be proved const 0 Winner of Hardware Model Checking Competition in 2008 and 2010Winner of Hardware Model Checking Competition in 2008 and 2010http://fmv.jku.at/hwmcc10/results.html D2 D1 Equivalence checking 0 D1 Property checking 0 p

Parallel Verification Framework How to use multiple cores to speed up verification?How to use multiple cores to speed up verification? Our approach is to run multiple engines on the same problemOur approach is to run multiple engines on the same problem If any of the engines succeeds, other engines are stoppedIf any of the engines succeeds, other engines are stopped The number of computation paths explored in parallel is exponential in the number of forksThe number of computation paths explored in parallel is exponential in the number of forks –Leads to speed up on most problem –Allows to solve hard, unsolved problems Optimization Try to verify Abstraction Try to verify Speculation Try to verify …

Synthesis Case Study: Using ABC in an Industrial Flow 10

Verification Case Study: Solving Hard Industrial Examples 11 Hard means that an industrial tool could not solve it in 2 hoursHard means that an industrial tool could not solve it in 2 hours –Mixture of equivalence and property checking examples 381 examples381 examples –228 hard examples –153 solved by tool –ABC results on hard examples 92 tried92 tried –55 solved –37 unsolved 136 not tried yet136 not tried yet

Future Work Developing and scaling bit-level methodsDeveloping and scaling bit-level methods Addressing bottlenecks in the synthesis flowAddressing bottlenecks in the synthesis flow –AIG rewriting –Choice computation –Technology mapping –Sequential synthesis Improving the verification flowImproving the verification flow –Application-specific, circuit-based SAT solving –Extracting and using word-level information –Exploiting synergies with synthesis