Wireless TXRX for TLL2020 It is awesome.

Outline Project Overview System Overview Transmiter Hardware Receiver Hardware FPGA Architecture Driver and Application References, Acknowledgments, and more baby pictures.

Project Overview Goal: To create a wireless physical front end for further study of digital communications theory and embedded system design.

Jason Perkey – Hardware Team (and project lead) Sarat Anumula – Hardware Team (and proud new father) Atif Habib – Software Team (verilog czar) Vanessa Canac – Software Team (code monkey) Division of Labor

System Block Diagram GPIOGPIO TX MX21 TLL6219 RX TLL5000 FPGA Accessory port Ribbon Cable Data Path Ribbon Cable2 Serial Communication & Control Signals MxFE Wireless “Our SRP*” * SRP = Software Radio Peripheral

TLL5000 Motherboard Accessory Port - Direct connection to FPGA - Datapath (transmit and receive data) - Master clock signal

TLL6219 Daughter Board CSPI Port and GPIO for control signals (for Mixer, VCO, and MxFE Processor)

Ettus USRP Motherboard Reference Design Motherboard

Ettus Daughterboard - RFX Reference Design Daughterboard

10 Digital Receiver Architecture: Partitioning Tasks Between hardware, fpga, and DSP H F A R R O D N W T A E R N E D ARM DSP FPGAFPGA *Slide adapted from Raghu Rao's Presentation 5/16/2009 VLSI Communications Lecture

BPSK & QPSK Modulation BPSK – One Bit / Symbol at a time QPSK – Two Bits / Symbols at a time on opposite clock phases I = In-phase clock Q = Quadrature phase

MxFE Processor

MxFE Processor - TX

Transmitter Path I - Channel Q - Channel Signals from FPGA. Mixed Signal front end processor Transmitter path – AD9860*. * AD9860 – Analog Devices

Tx to Up-converter. To Mixer. From FPGA clock.

TX to Upconverter. From FPGA From Local Oscillator To Antenna RF_TX High Gain Block MMIC Amplifier High Linearity Amplifier.

RF_TX Transmit Antenna & LPF

RX Path – to IF LNA Mixer Single-Ended to Differential Conversion Variable Gain Control – Output from AD9860 I Q LO

RX – LO Generation Clock_P from FPGA Synthesizer and VCO Synthesizer and VCO – Digital Control Serial Communication from MX21 CSPI (GPIO Ribbon Cable) To Mixer

RX – IF to ADC I Q To FPGA Data-In Mixed-Signal Front-End Processor Receiver Path, AD9860

MxFE Processor

The Verilog Serves as the interface between Hardware and Software Uses a FIFO protocol for bus transactions Separate FIFO Registers are kept for RX and TX data Initiates interrupts to indicate FIFO status Utilizes the BPSK algorithm for modulation/demodulation of data

Block Diagram

Current Status FIFO protocol for Bus Interactions completed –Includes Interrupt generation BPSK algorithm code still under development –Will be completed over the Summer of 2009

Software Block Diagram (vanessa)

Driver Initialize and setup wireless board through the CSPI2 port Will use an interrupt to warn when FIFO's are nearing empty/full ioctl command + purpose –TX_COMMAND – write to transmission FIFO –RX_COMMAND – read from receive FIFO –CHK_TX_COMMAND – request number of entries in transmission FIFO –CHK_RX_COMMAND – request number of entries in receive FIFO

Driver Progress Interrupt implemented. Policy for software to access transfer and receive FIFO's implemented. Need to write the initialization routine for the wireless hardware.

Software Completed work: –Partial testing of driver completed. –Can read and write to files. Work Remaining: –Complete driver testing. –Determine and implement a transmission protocol.

Summary – Into the Summer Finish board design Simulate passive on-board networks Determine ECC and clock recovery strategy Tapeout and commission board assembly Complete Verilog and Software development Debug, debug, debug, … Profit! –(by “profit” we mean write a master's report)

Acknowledgements and References Mark McDermott, TA's, Adnan Aziz, phd students that showed us their Ettus boards. Gnuradio software. ( Reference design adapted from open source project at: