Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 4 Robert Mars

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Expected Differences frequency ↓ due to wire delay power ↑ due to wire capacitance Considered Floorplan optimizations: Aspect Ratio Utilization Slide 2

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Aspect Ratio Slide 3

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Utilization Slide 4

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Further Optimization Routing: Optimize Via Optimize Wire Timing Driven 5 Optimize Design Timing Effort High Leakage Power Effort High Dynamic Power Effort High Slide 5

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Mandatory values for ASIC Phase 3Phase 4 Timing (T min / f max ) 1923 ps/ 520 MHz 2212 ps/ 452 MHz Power (P dyn / P leak ) 1,5195 mW / 15,1019 nW 1,088 mW / 14,7724 nW # Pipeline Stages 22 Benchmark 1,1784E+281,2712E+28 Core size2706 Core utilization75,9 % Slide 6

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention Slide 7

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Pads Slide 8 Mandatory values for ASIC Pads Timing (T min / f max ) 1209 ps/ 827 MHz Power (P dyn / P leak ) 95,414 mW / 6,273 mW # Pipeline Stages 2 Benchmark 1,1427E+21 99,77% power consumption by pads!