Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: September 27, 2013 Variation

Previously Understand how to model transistor behavior Given that we know its parameters –V dd, V th, t OX, C OX, W, L, N A … Penn ESE370 Fall DeHon 2 C GC C GCS C GCB

But… We don’t know its parameters (perfectly) 1.Fabrication parameters have error range 2.Identically drawn devices differ 3.Parameters change with environment (e.g. Temperature) 4.Parameters change with time (aging) Why I am more concerned with robustness than precision. Penn ESE370 Fall DeHon 3

Today Sources of Variation –Fabrication –Operation –Aging Coping with Variation –Margin –Corners –Binning Penn ESE370 Fall DeHon 4

Fabrication Penn ESE370 Fall DeHon 5

Variation Types Many reasons why things are different –Show up in many different ways. Scales –Wafer-to-wafer, die-to-die, transistor-to- transistor Correlations –Systematic, spatial, random (uncorrelated) Penn ESE370 Fall DeHon 6

7 Source: Noel Menezes, Intel ISPD2007

Process Shift Oxide thickness Doping level Layer alignment Growth and Etch rates and times –Depend on chemical concentrations How precisely can we control those? Vary machine-to-machine, day-to-day Impact all transistors on wafer Penn ESE370 Fall DeHon 8

Systematic Spatial Parameters change consistently across wafer or chip based on location Chemical-Mechanical Polishing (CMP) –Dishing Lens distortion Penn ESE370 Fall DeHon 9

FPGA Systematic Variation 65nm Virtex 5 Penn ESE370 Fall DeHon 10 [Tuan et al. / ISQED 2010]

Penn ESE370 Fall DeHon 11 Oxide Thickness [Asenov et al. TRED 2002]

Penn ESE370 Fall DeHon 12 Line Edge Roughness 1.2  m and 2.4  m lines From:

Optical Sources What is the shortest wavelength of visible light? How compare to 45nm feature size? Penn ESE370 Fall DeHon 13

Penn ESE370 Fall DeHon 14 Phase Shift Masking Source Today’s chips use λ =193nm

Penn ESE370 Fall DeHon 15 Line Edges (PSM) Source:

Penn ESE370 Fall DeHon 16 Intel 65nm SRAM (PSM) Source:

Penn ESE370 Fall DeHon 17 Statistical Dopant Placement [Bernstein et al, IBM JRD 2006]

Random Trans-to-Trans Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates –Stochastic process Transistors differ from each other in random ways Penn ESE370 Fall DeHon 18

Penn ESE370 Fall DeHon 19 Source: Noel Menezes, Intel ISPD2007

Impact Changes parameters –W, L, t OX, V th Change transistor behavior –W? –L? –t OX ? Penn ESE370 Fall DeHon 20

Example: V th Many physical effects impact V th –Doping, dimensions, roughness Behavior highly dependent on V th Penn ESE370 Fall DeHon 21

Penn ESE370 Fall DeHon 22 V th 65nm [Bernstein et al, IBM JRD 2006]

Penn ESE370 Fall DeHon 23 Impact of V th Variation? Higher V TH ? –Not drive as strongly –I d,vsat  (V gs -V TH ) –Performance?

Impact Performance V th  I ds  Delay (R on * C load ) Penn ESE370 Fall DeHon 24

Impact of V th Variation Penn ESE370 Fall DeHon 25 Think NMOS Vgs = Vdd

FPGA Logic Variation Xilinx Virtex 5 65nm Penn ESE370 Fall DeHon 26 [Wong, FPT2007] Altera Cyclone-II 90nm [Tuan et al. / ISQED 2010]

Variation in 65nm FPGAs 27 [Gojman, FPGA2013] DeHon May 2013

LUT-to-LUT Same LAB 28 LAB (27,22) average 5% variation DeHon May 2013 [Gojman, FPGA2013]

Delay Map LAB (27,22) DeHon May [Gojman, FPGA2013]

Two LUT2LUT across Chip DeHon May

Reduce Vdd (Cyclone IV 60nm LP) DeHon May [Gojman, FPGA2013]

Penn ESE370 Fall DeHon 32 Impact of V th Variation? Lower V TH ? –Not turn off as well  leaks more

Penn ESE370 Fall DeHon 33 Borkar (Intel) Micro 37 (2004) 2004

Operation Temperature Voltage Penn ESE370 Fall DeHon 34

Temperature Changes Different ambient environments –January in Maine –July in Philly –Air conditioned machine room Self heat from activity of chip Quality of heat sink (attachment thereof) Penn ESE370 Fall DeHon 35

Self Heating Penn ESE370 Fall DeHon 36 Borkar (Intel) Micro 37 (2004)

Thermal Profile for Processor Penn ESE370 Fall DeHon 37 [Reda/IEEE Tr Emerging CAS v1n2 2011]

How does temperature impact on-current? High temperature –More free thermal energy Easier to conduct Lowers V th –Increase rate of collision Lower saturation velocity Lower saturation voltage Lower peak I ds  slows down One reason don’t want chips to run hot Penn ESE370 Fall DeHon 38

Temperature and I ds Penn ESE370 Fall DeHon 39

How does temperature impact leakage current? High temperature Lowers V th Penn ESE370 Fall DeHon 40

Voltage Power supply isn’t perfect Differs from design to design –Board to board? –How precise is regulator? IR-drop in distribution Bounce with current spikes Penn ESE370 Fall DeHon 41

Aging Hot Carrier NBTI Penn ESE370 Fall DeHon 42

Hot Carriers Trap electrons in oxide –Also shifts V th Penn ESE370 Fall DeHon 43

NBTI Negative Bias Temperature Instability –Interface traps, Holes Long-term negative gate-source voltage –Affects PFET most Increase V th Partially recoverable? Temperature dependent Penn ESE370 Fall DeHon 44 [Stott, FPGA2010] Another reason not to run hot.

Measured Accelerated Aging (Cyclone III, 65nm FPGA) Penn ESE370 Fall DeHon 45 [Stott, FPGA2010]

Coping with Variation Penn ESE370 Fall DeHon 46

Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Penn ESE370 Fall DeHon 47

Penn ESE370 Fall DeHon 48 Impact of V th Variation Higher V TH –Not drive as strongly –I d,vsat  (V gs -V TH ) Lower V TH –Not turn off as well  leaks more

Penn ESE370 Fall DeHon 49 Variation Margin for expected variation Must assume V th can be any value in range –Speed  assume V th slowest value Probability Distribution V TH I on,min =I on (V th,max ) I d,vsat  (V gs -V th )

Gaussian Distribution Penn ESE370 Fall DeHon 50 From:

Impact Given –V th,nom = 250mV –Sigma 25mV Probability of 100 transistor circuit in range when each has 96% prob. ? …when each has 99.8% probability? Penn ESE370 Fall DeHon 51

Impact Given –V th,nom = 250mV –Sigma 25mV What maximum V th should expect to see for a circuit of –100 transistors? –1000 transistors? –10 9 transistors? Penn ESE370 Fall DeHon 52

Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Validate design at extremes –Work for both V th,min and V th,max ? –Design for worst-case scenario Penn ESE370 Fall DeHon 53

Margining Also margin for –Temperature –Voltage –Aging: end-of-life Penn ESE370 Fall DeHon 54

Process Corners Many effects independent Many parameters With N parameters, –Look only at extreme ends (low, high) –How many cases? Try to identify the {worst,best} set of parameters –Slow corner of design space, fast corner Use corners to bracket behavior Penn ESE370 Fall DeHon 55

Simple Corner Example Penn ESE370 Fall DeHon 56 Vthp Vthn 150mV 350mV What happens at various corners?

Process Corners Many effects independent Many parameters Try to identify the {worst,best} set of parameters –E.g. Lump together things that make slow Vthn, Vthp, temperature, Voltage Try to reduce number of unique corners –Slow corner of design space Use corners to bracket behavior Penn ESE370 Fall DeHon 57

Range of Behavior Still get range of performances Any way to exploit the fact some are faster? Penn ESE370 Fall DeHon 58 Probability Distribution Delay

Penn ESE370 Fall DeHon 59 Speed Binning Probability Distribution Delay Discard Sell Premium Sell nominal Sell cheap

Idea Parameters Approximate Differ –Chip-to-chip, transistor-to-transistor, over time Robust design accommodates –Tolerance and Margins –Doesn’t depend on precise behavior Penn ESE370 Fall DeHon 60

Midterm 1 Contents should not be a surprise –Identify CMOS/non-CMOS –Identify CMOS function –Any logic function  CMOS gate –Noise Margins –Circuit quasistatic configuration and switching delay Penn ESE370 Fall DeHon 61

Admin Midterm Monday –7—9pm in Towne 309 Previous midterm –Solutions linked to syllabus But only one midterm in 2010 so parts more advanced than where we are now Review on Sunday –5:30pm Penn ESE370 Fall DeHon 62