Standard Cell Libraries

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Presentation transcript:

Standard Cell Libraries -- Presentation by Abhay Dixit Meeta Bhate Kedar Rajpathak

What are Standard Cell Libraries Standard-cell libraries are fixed set of well-characterized logic blocks. Basic logic functions are used several times on the same integrated circuit. It will have leaf cells ranging from simple gates to latches and flip-flops. These can then be used to build arithmetic blocks like adders and multipliers. ASIC designers commonly employ the use of standard cell libraries due to their robustness and flexibility resulting in quick turnaround times.

Advantages of standard cell libraries Designers save time and money by reducing the product development cycle time. Reduce risk by using predesigned, pretested and precharacterised standard cell libraries. Optimisation is possible.

Disadvantages of standard cell libraries Time and expenses of designing or buying the standard cell library. Time needed to fabricate all layers of ASIC for each new design when the standard cell library must be ported to a new fabrication process, the physical layout of all the cells need to be changed. There are no naming conventions There are no standards for cell behavior

Classification of standard cell libraries Classical Libraries: --- Theses are the most common logic elements like gates, flip-flops, multiplexers, PAL, memories etc. IP (Intellectual Property) offerings: --- These include products like gate arrays and CPLDs which are IP offerings by many companies. Each one providing its own features and facilities in the product.

Fragment of an ASIC Library

MOSIS compatible design tools and cell libraries MOSIS compatible cell libraries are provided by many organisations, commercial and non-commercial both Commercial organisations are: Mentor Graphics, Cadence, Artisan, Avant, Barcelona Design, Tanner Research, LEDA systems etc. Non Commercial Organisations are:MSU’s SCMOS Library, LASI, Ballistic, Magic etc.

Standard Cells Provided by Mentor Graphics There are over 200 standard cells available for the 2.0 um, 1.2 um, and 0.8 um technology. -- 2, 3, and 4-input AND, NAND, OR, NOR, AO -- 2-input XOR and XNOR gates -- 2-1 MUX gate -- multiple drive strength buffers, inverters and tri-state buffers -- four D-type flip-flops: dff, dffs, dffr, and dffsr -- four D-type latches: latch, latchs, latchr, latchsr All of these cells have quickpart models with timing for full, backannotated simulation after layout

MGC Digital Libraries

MGC Digital Libraries (Contd..)

MGC Digital Libraries (Contd..)

MGC Digital Libraries (Contd..)

MGC Digital Libraries (Contd..)

MGC Digital Libraries (Contd..) * 07/16/96 MGC Digital Libraries (Contd..) *

New Trends in Standard Cell Libraries In a bid to improve the performance of standard-cell designs, vendors of place-and-route and synthesis tools and cell libraries are teaming up to develop a technique that is likely to lead to the death of the standard cell itself. Prolific Inc. (Newark, Calif.) has launched a tool called Liquid Libraries that will create tuned cells on the fly and insert them into the libraries used by place and route tools Hot on the heels of Prolific's launch, Cadabra Design Automation (Santa Clara, Calif.) is working on a new flow that would ultimately move library generation as far forward as the synthesis phase, giving logic designers the ability to tune parts of a design for low power consumption or speed

New Trends Contd.. Prolific is working with Cadence Design Systems, Magma Design Automation, Monterey Design Systems and Sapphire Design Automation.. Cadabra is working with Avanti, Cadence, Synopsis and Magma. The first fruit of the Cadabra project will be the power and performance optimization (PPO) flow.

Important Links to Standard Cell Libraries a) Tanner Inc. www.tanner.com. b) Prolific Inc. www. prolificinc.com c) MOSIS organisation www.mosis.org MOSIS/Tech Support/MOSIS Compatible Design Tools d) Cadabra Design www.cadabratech.com Automation Inc. e) Cadence Design Systems www.cadence.com Inc.

Thank You