IPC-SM-782 Soldermask vs. Lands Only

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Presentation transcript:

IPC-SM-782 3.7.1 Soldermask vs. Lands Only In referring to the outer layers of the multilayer PB, there is a dramatic difference between the concepts of soldermask and having no conductors on the outer layers.

IPC-SM-782 3.7.1 Soldermask vs. Lands Only Conventional SMT design rules allow routing conductors on the outer layers, running the conductors between Surface Mount lands, then applying soldermask to cover the conductors and leave the lands exposed. For high density SMT applications, the conductors and clearances on the outer layers are generally in the 0.15-0.2 mm [0.006-0.008 in] range.

IPC-SM-782 3.7.1 Soldermask vs. Lands Only Aside from the soldermask registration, maintaining precision conductor width control on the outer layers is significantly more difficult than on the inner layers. Outer layer conductor integrity can be a cause of poor fabrication yields.

IPC-SM-782 3.7.1 Soldermask vs. Lands Only The soldermask rule is very simple: the conductors between lands must be covered with soldermask, while the lands must not have any soldermask on them. When using smaller geometries, adding the Standard Fabrication Allowance of 0.2 mm [0.008 in] can make soldermask registration very difficult.

IPC-SM-782 3.7.1 Soldermask vs. Lands Only Given the two distinct yield difficulties of conductor width control and soldermask application, board manufacturers with experience in high density SMT printed conductor boards may favor the lands only (pad cap) concept. The pad cap concept has two yield improvement benefits:

IPC-SM-782 3.7.1 Soldermask vs. Lands Only 1) no fine conductor geometries on the outer layers because they are buried in the inner layers where conductor width control is significantly easier, and 2) the need for soldermask is reduced or eliminated because there are no small spaces to protect from the soldering process.

IPC-SM-782 3.7.1 Soldermask vs. Lands Only In general, an 8-layer printed board, with lands only on the outer layer, is similar in cost to a 6-layer printed board with solder mask, assuming both have SMT geometries. The primary reason for this is that some PB fabricators are realizing about a 12% yield improvement by not having the fine line conductors on the outer layers.

IPC-SM-782 3.7.1 Soldermask vs. Lands Only The benefits of pad caps continue into the assembly process by increasing yields through the reduction of solder shorts or bridging. The pad cap concept provides 100% testability, thus testing benefits are both economical and practical.