Computer Organization CS224 Fall 2012 Lessons 47 & 48

Introduction  I/O devices can be characterized by l Behaviour: input, output, storage l Partner: human or machine l Data rate: bytes/sec, transfers/sec  I/O bus connections §6.1 Introduction

I/O System Characteristics  Dependability is important l Particularly for storage devices  Performance measures l Latency (response time) l Throughput (bandwidth) l Desktops & embedded systems -Mainly interested in response time & diversity of devices l Servers -Mainly interested in throughput & expandability of devices

Dependability  Fault: failure of a component l May or may not lead to system failure §6.2 Dependability, Reliability, and Availability Service accomplishment Service delivered as specified Service interruption Deviation from specified service FailureRestoration

Dependability Measures  Reliability: mean time to failure (MTTF ) Fig 6.5)  Service interruption: mean time to repair (MTTR)  Mean time between failures l MTBF = MTTF + MTTR  Availability = MTTF / (MTTF + MTTR)  Improving Availability l Increase MTTF: fault avoidance (↑ quality), fault tolerance (w/ redundancy), fault forecasting (replace before failure) l Reduce MTTR: improved tools and processes for diagnosis and repair

Disk Storage  Nonvolatile, rotating magnetic storage §6.3 Disk Storage

Disk Sectors and Access  Each sector records l Sector ID l Data (512 bytes, 4096 bytes proposed) l Error correcting code (ECC) -Used to hide defects and recording errors l Synchronization fields and gaps  Access to a sector involves l Queuing delay if other accesses are pending l Seek: move the heads l Rotational latency (0.5 rotation, on average) l Data transfer l Controller overhead

Disk Access Example  Given l 512B sector, 15,000rpm, 4ms average seek time, 100MB/s transfer rate, 0.2ms controller overhead, idle disk  Average read time l 4ms seek time (c.f. mfg data sheet) + ½ / (15,000/60) = 2ms rotational latency + 512B / 100MB/s = 0.005ms transfer time + 0.2ms controller delay = 6.2ms  If actual average seek time is 1ms l Average read time = 3.2ms

Disk Performance Issues  Manufacturers quote average seek time l Based on all possible seeks l Locality and OS scheduling lead to smaller actual average seek times  Smart disk controller allocate physical sectors on disk l Present logical sector interface to host l SCSI, ATA, SATA  Disk drives include caches l Pre-fetch sectors in anticipation of access l Avoid seek and rotational delay

Flash Storage  Nonvolatile semiconductor storage l 100× – 1000× faster than disk l Smaller, lower power, more robust l But more $/GB (between disk and DRAM) §6.4 Flash Storage

Flash Types  NOR flash: bit cell like a NOR gate l Random read/write access l Used for instruction memory in embedded systems  NAND flash: bit cell like a NAND gate l Denser (bits/area), but block-at-a-time access l Cheaper per GB l Used for USB sticks, media storage, …  Flash bits wear out after 1000’s of accesses l Not suitable for direct RAM or disk replacement l Wear leveling: remap data to less used blocks

Interconnecting Components  Need interconnections between l CPU, memory, I/O controllers  Bus: shared communication channel l Parallel set of wires for data and synchronization of data transfer l Can become a bottleneck  Performance limited by physical factors l Wire length, number of connections  More recent alternative: high-speed serial connections with switches l Like networks §6.5 Connecting Processors, Memory, and I/O Devices

Bus Types  Processor-Memory buses l Short, high speed l Design is matched to memory organization  I/O buses l Longer, allowing multiple connections l Specified by standards for interoperability l Connect to processor-memory bus through a bridge

Bus Signals and Synchronization  Data lines l Carry address and data l Multiplexed or separate  Control lines l Indicate data type, synchronize transactions  Synchronous l Uses a bus clock  Asynchronous l Uses request/acknowledge control lines for handshaking

I/O Bus Examples FirewireUSB 2.0PCI ExpressSerial ATASerial Attached SCSI Intended useExternal Internal External Devices per channel Data width422 per lane44 Peak bandwidth 50MB/s or 100MB/s 0.2MB/s, 1.5MB/s, or 60MB/s 250MB/s/lane 1×, 2×, 4×, 8×, 16×, 32× 300MB/s Hot pluggable Yes DependsYes Max length4.5m5m0.5m1m8m StandardIEEE 1394USB Implementers Forum PCI-SIGSATA-IOINCITS TC T10

Typical Intel Server w/ I/O System

I/O Management  I/O is managed by the OS l Multiple programs share I/O resources -Need protection and scheduling l I/O causes asynchronous interrupts -Needs same mechanism as exceptions l I/O programming is detailed and complex -OS provides abstractions to programs -OS handles details in I/O subsystem §6.6 Interfacing I/O Devices …

I/O Commands  I/O devices are managed by I/O controller hardware l Transfers data to/from device l Synchronizes operations with software  Command registers l Cause device to do something  Status registers l Indicate what the device is doing and occurrence of errors  Data registers l Write: transfer data to a device l Read: transfer data from a device

I/O Register Mapping  Memory mapped I/O l I/O command, status and data registers are addressed in same space as memory l Address decoder distinguishes between them, sends to request to memory or to I/O l OS uses address translation mechanism to make them only accessible to kernel  I/O instructions l Separate instructions to access I/O registers l Can only be executed in kernel mode l Example: x86

Polling  Periodically check I/O status register l If device ready, do operation l If error, take action  Common in small or low-performance real-time embedded systems l Predictable timing l Low hardware cost l Usually just one process  In other systems, this waste of CPU time is undesirable

Interrupts  When a device is ready or error occurs l Controller interrupts CPU  Interrupt is like an exception l But not synchronized to instruction execution l Can invoke OS handler between instructions l Cause information often identifies the interrupting device  Priority interrupts l Devices needing more urgent attention get higher priority l Can interrupt handler for a lower priority interrupt

I/O Data Transfer  Polling and interrupt-driven I/O l CPU transfers data between memory and I/O data registers l Time consuming for high-speed devices  Direct memory access (DMA) l OS provides starting address in memory l I/O controller transfers to/from memory autonomously l Controller interrupts on completion or error l While DMA uses memory, processor uses cache; both can operate in parallel (in the ideal)

DMA/Cache Interaction  If DMA writes to a memory block that is cached l Cached copy becomes stale  If write-back cache has dirty block, and DMA reads memory block l Reads stale data  Need to ensure cache coherence l Flush blocks from cache if they will be used for DMA l Or use non-cacheable memory locations for I/O