March OsC Report and Restructuring WP4

OsC Report 4.1 Tapes Bus tape designs have been completed for modules with 130nm ASICs which incorporate options for both DCDC and SP powering within the same tape design (4.1). The tape contains two copper layers with the top copper layer used for some high voltage (HV) and low voltage tracks as well as the ground referencing. This allows us to respect the HV clearance specifications and to design a tape which could be used for both serial power and with DC-DC converters. The shield layer has been being iterated over the last three tape designs and now is very localised and performs more as a ground plane. Progress on the robotic tape tester is being made. A full-scale alignment artefact has been manufactured and measured at Liverpool and has been used to understand the coordinate-system calibration.

OsC Report 4.2 Stave Core Assembly The design-phase for the next iteration of 13-module long stave cores for 130nm ASICs is nearing completion. Time has been taken to incorporate feedback and ideas from across the international community and inevitably this has led to some delays. Initial designs of the various pieces of tooling needed to manufacture these stave cores has been developed and these are now being integrated, together with the stave core, into a single 3D model to ensure compatibility. The manufacture of low-level parts for the stave assembly tool, which are independent of geometry (eg. Inserts, close-out corners, etc) are being manufactured. It is hoped that the design work will be completed in time for the Freiburg meeting at which it will be reviewed leading to the start of manufacture just in May.

OsC Report 4.3 Module Mounting The mounting of modules to the first 12-module stave, completed at RAL in November 2013, constitutes a major deliverable to the international strip tracker programme. It is widely acknowledged that module mounting and wire bonding proceeded smoothly and with no damaged modules. The experience gained is currently being reviewed and the development of the module pick-up tools needed for the 130nm modules has commenced. Currently, module mounting for the next 12-module serial-powered stave has commenced but this work is now on hold pending the completion of the initial electrical testing programme on 130nm ASICs.

Re-structuring Why? – Groups are putting greater effort into WP2 than was assumed 2 years ago – Knock-on from delays to the ASIC programme – Alignment task dropped in cost-cutting exercise – Impact of HVCMOS Whatever we do we need to tell the OsC.. – Mention all of above – Say we should have completed the stave core design and assembly tooling design & manufacture and be in a position to manufacture stave cores by end or September

Re-structuring The impact of delays in the delivery of fully functional 130nm ASICs (and the consequent availability of 130nm electrical modules) on the future deliverables from WP4 are in the process of being evaluated. Currently we believe that the manufacture of a large number of pre- production module-ready stave cores will be beyond the end of this current grant period. Consequently, not all the effort associated with updating the final stave engineering design, the design and manufacture of the stave assembly tooling, and the development of the final assembly and test procedures will be used. This raises the possibility of redeploying this effort into other parts of the project. Already a limited amount of effort has been redeployed to pixel mechanics and integration (WP2 and WP6) and is being used to cement the UK groups’ leadership in the mechanical development of the endcap pixel system. We are now looking to reinstate the tracker alignment task that was removed in the trimming of the project to the funding envelope but we had aspired to fund through WA should the opportunity arise. However, we are also conscious that there may be a call to contribute mechanical effort to evaluate the impacts of adopting HVCMOS technology. As the initial work on alignment will not begin until the core production and tooling programme is complete we intend to complete this evaluation of HVCMOS vs alignment during the summer with the aim of committing this effort from October 2014.