First ideas for the Argontube electronics Shaper, simulations Block Diagram for analog path Delta Code Data Reduction Bus system, Controller Max Hess CERN

Scheme for simulation

Shaper, differentiation V pre  = 5  s  = 10  s without pole zero cancellation

Shaper, differentiation and integration  dif = 10  s with:  int = 500 ns  int = 1  s  dif = 5  s with:  int = 500 ns  int = 1  s

Block Diagram for analog path Max Hess U PRE Charge amplifier -U S +U S Shaper offset U ADC DAQ analog input stage ADC CFCF RFRF CDCD CICI RDRD R PZ RIRI RIRI RIRI RIRI R I = 1kTwisted pair flat cable shielded

Delta Code ADC ∆ coder circular buffer DRAM 32 bit x 8 computer or 4 MHz 32 1 MS/s, 12 bit ∆ code : S n – S n-1 if S n – S n else 4 bit 1 1 S n 1 bit serial ADC ∆ coder circular buffer Max Hess

Block Diagram for Data Reduction INPUT BUFFER (SRAM) DATA REDUCTION LOGIC OUTPUT FIFO (DRAM) IN 7 IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII Max Hess TRIGGER DATA 16 or 32 MEMORY CONTROLLER addr BACK PLANE BUS 12 1 SHIFT REG MUX REG WRITE ADDRESS COUNTER READ ADDRESS COUNTER TRIGGER ADDRESS REGISTER I / O CONTROLLER MUX ADC IN 0 SHIFT REG ADC 16 or 32 FPGA: Altera APEX 20K family FPGA Cypress CY7C1011CV33 tacc: 15 ns 360 mW 44-pin TQFP National Semiconductors ADC121S bit, 1MS/s 2 mW 6-lead LLP

Timing for ADC and Input Buffer Z2Z1Z0D11 msb D10 D0 lsb D0 lsb 8 write cycles 12 read cycles are possible CLK WEn TRACK & HOLD SDATA LD REG ADC sample = 1  s 50ns Max Hess

Organisation of Input Buffer MEMORY BANK A WITH 8 SECTORSMEMORY BANK B WITH 8 SECTORS Memory = SRAM 128k x 16 bit / 2 memory banks with 8 sectors / 1 sector = 8k x 16 bit / Write mode: 8 sectors work as circular buffers Read mode: readout of one sector after another Write cycles in the memory bank A at the begin of the write sequence Sn CH0Sn CH Write cycles in the memory bank A, nearly at the end of the write sequence Write cycles in the memory bank B at the begin of the write sequence, read all data of sector 0, then 1, 2 etc. Sn CH7 read Write cycles in the memory bank B at the middle of the write sequence, read of the last data in sector Max Hess

n post n pre Frame 1 t1 n pre Frame 2 t2 trigger input (NIM) n post digital comparator thershold t0=0 n pre trigger Create frames p Max Hess

Create frames p Max Hess n post n pre Frame 1 t1 n pre trigger input (NIM) n post digital comparator threshold t0=0 n pre trigger

Data format, overview bit Control bits:3 bit Modul address111xxxxxxxmmmmmm Event number0eeeeeeeeeeeeeee Channel number110xxxxxxxx2 bits3 bits Time stamp101ttttttttttttt End of record100xxxxxxxxxxxxx Data0xxxdddddddddddd Aquisition mode: Full readout11011 Frame11001 inhibit Max Hess

Data format, example p 1 / 2 bit Modul address111xxxxxxxmmmmmm Event number0eeeeeeeeeeeeeee Channel 0 with data reduction, generate frames with samples over the digital threshold 0: aq mode + ch no.110xxxxxxxx : frame 1, time stamp101ttttttttttttt 0: frame 1, data0000dddddddddddd :::::: 0000dddddddddddd 0: frame 2, time stamp101ttttttttttttt 0: frame 2, data0000dddddddddddd :::::: 0000dddddddddddd :::::: 0: frame n, time stamp101ttttttttttttt 0: frame n, data0000dddddddddddd :::::: 0000dddddddddddd

Data format, example p 2 / 2 bit : frame n, data0000dddddddddddd :::::: Channel 1 with data reduction, generate no frames, because no samples exceed the digital threshold 1: aq. mode + ch no.110xxxxxxxx01001 :::::: Channel 2 with full readout 2: aq. mode + ch no.110xxxxxxxx : frame 1, time stamp101ttttttttttttt 2: frame 1, data (0)0000dddddddddddd :::::: :::::: 2: frame 1, data (8191)0000dddddddddddd :::::: :::::: Channel 7 inhibited, only the header will generated 7: aq. mode + ch no.110xxxxxxxx00111 End of record100xxxxxxxxxxxxx

Used output memory per event Max Hess with Data Reduction, 1 pulse include 40 samples # pulses / channel kBytes for 8 channels

Bus system, Controller CONTROLLER 8 channels 16 DAQ cards = 128 channels / sub system INTERFACE Ethernet to Host Max Hess

DAQ Card, auxiliary I/O Inputs:Trigger Clear Output:Buffer Full Max Hess Interconnections to other logic ? NIM level: inputs hi-z, 2 connectors, outputs with 2 connectors or flat cable with bus configuration to interface board