Instructor: Yuzhuang Hu

Midterm The midterm is schedule on June 17 th, 17:30-19:30 pm. It covers the following:  VHDL Programming.  Number Systems.  Sequential Circuit Design. This includes State-Machine Diagrams, ASM chart, control unit, data path, etc.  The Simple Single-Cycle Computer. Its Datapath, the Control Word, Instruction Formats, Single Cycle Hardwired Control, etc.

Block Diagram for a Single-Cycle Computer

Instruction Specifications for the Simple Computer

Control Unit of the Single Cycle Simple Computer We have described the design of its datapath. The block diagram for this computer has a hardwired control unit that fetches and executes an instruction in a single clock cycle. We do not write to the instruction memory, making it appear in this model to be a combinational rather than a sequential component.

The Program Counter (PC) The PC provides the instruction address to the instruction memory. The PC is updated in each clock cycle. The behaviour of the PC is determined by the opcode, N, and Z. PC OperationPLJBBC Count Up0XX Jump11X Branch on Negative (else Count Up)101 Branch on Zero (else Count Up)100

Instruction Decoder The instruction decoder is a combinational circuit that provides all of the control words for the datapath, based on the contents of the fields of the instruction. TruthTable for Instruction Decoder Logic Instruction Function Type Instruction BitsControlWord Bits MBMDRWMWPLJBBC Function unit operations using registers 0 0 0X X Memory read 0 01X X Memory write 0 10X 0 X 0 10X Function unit operations using register and constant 1 0 0X X Conditional branch on zero (Z) 1100 X X Conditional branch on negative (N) 1101 X X Unconditional Jump 111X X X

Instruction Decoder contd. The 13 th, 14 th and 15 th bits of the instruction are set to 1 respectively, to distinguish the memory read, memory write and constant involved instructions from the register only instructions. For this reason MB=15 th bit, MD=13 th bit, and the 14 th bit is involved in generating MW. There is some additional logic to prevent RW and MW to be 1 at the same time.

Instruction Decoder contd. The 15 th bit of the instructions is used mainly for jumping and branching instructions. However to distinguish them from the instructions involving constants, the 14 th bit is also needed to generate PL. BC uses the 9 th bit. JB uses the 13 th bit, however as PL=1 when JB=1, there is no conflict with MD. For conditional branching, it is required that FS=0000. That’s the reason PL is involved in generating FS.

Instruction Decoder Logic

Sample Instructions  Six Instructionsfor theSingle-Cycle Computer Operation code Symbolic nameFormatDescriptionFunctionMBMDRWMWPLJBBC ADIImmediateAdd immediate operand LDRegisterLoad memory content into register STRegisterStore register content in memory SLRegisterShift left NOTRegisterComplement register BRZJump/BranchIfR[SA]= 0, branch to PC+ se AD If R[SA] = 0,, If R[SA]  0, RDR  RSA  zfI(2:0) +  RDR  M RSA  M RSARSB  RDR  slRSB  RDR  RSA  PCPCseAD +  PC 1 + 

Shortcomings of the Single-Cycle Computer The single cycle computer can not perform more complex operations. For example, unsigned binary multiplications. The single cycle computer has two distinct 16-bit memories, one for instructions and one for data. Every instruction, no matter it is simple or complex (e.g., jmp), is executed in a clock cycle. Therefore It has a lower limit on the clock period.

Worst-Case Delay Path in Single- Cycle Computer PC Instruction Memory Register File (Read) MUX B FU or Data Memory Register File (Write) MUX D 0.2 ns

Store Instructions and Data in a Single Memory Datapath : a single memory, and an MUX M. Add 8 temporary registers to the register file. Control Unit:  Instruction Register (IR) to store the instruction fetched from the memory.  Control State. The control unit is now a sequential circuit.  Control Logic : different control words. Branch logic is moved to here.

Control Word Format for Multi- Cycle Computer The addressing of the registers needs 4 bits (DX, AX, BX). NSPS I L M B M D R W M M M W DX AXBXFS Datapath Sequencing NSPSIL Next StateActionCodeActionCode Gives next state of Control State Register Hold PC00No load0 Inc PC01Load IR1 Branch10 Jump11 Sequence Control NS: next state PS: control PC IL: control IR

Sequential Control Design Now the computer has two stages: instruction fetch (INF stage) and instruction execution (EX0 stage). IR Register File (Read) MUX B FU or Data Memory Register File (Write) MUX D 0.2 ns PC MUX M Memory IR 0.2 ns INFEX0

Instruction Specifications

Partial State Machine Diagram for Multiple-Cycle Computer

Deriving Logic Expressions For PC <- PC +1, we must set PS to 01. We can write PS(0) = EX0·MOVA + EX0 ∙ INC + EX0 ∙ ADD + … + EX0·BRZ·(not Z). Each combination of state, opcode, and condition codes where the signal should be 1 introduces a product term to the final expression.

Multiplication in the Multiple-Cycle Computer For simple instructions, we need more time to finish them in the multi-cycle computer. Multiplication shows the advantage.  Assume multiplication in the function unit needs 10 ns. For the single cycle-cpu, the clock cycle must be increased to 15.8 ns.  The clock cycle would remain 5.8 ns, if we give one more clock cycle for multiplication.

State Diagram for Multiplication INF IR <- M[PC] EX0 Multiply R[SA]*R[SB] IMUL1 R[DR] <- R[SA]*R[SB], PC <- PC + 1

Register Indirect Instructions R[DR] <- M[M[R[SA]]]. INF IR <- M[PC] EX0 Opcode = R8 <- M[R[SA]] EX1 Opcode = R[DR]<-R8, PC <- PC+1

Partial State Machine Diagram for Right- Shift and Left-Shift Multiple Instructions

Micro-programmed Control A control unit with its binary control values stored as words in memory is called a micro-programmed control. Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system. The micro-program is usually fixed at the system design time and so is stored in ROM.

CAR: Control Address Register.

THANKS!