Page 1EL/CCUT T.-C. Huang May 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech /05/10
Page 2EL/CCUT T.-C. Huang May 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability
Page 3EL/CCUT T.-C. Huang May 2004 TCH CCUT Built-In Self-Test (BIST) Objectives 1.To Reduce input/output pin signal traffic. 2.Permit easy circuit initialization and observation. 3.Eliminate as much test pattern generation as possible. 4.Achieve fair fault coverage on general class of failure mode. 5.Reduce test time. 6.Execute at-speed testing. 7.Test circuit during burn-in.
Page 4EL/CCUT T.-C. Huang May 2004 TCH CCUT 1.Area overhead 2.Performance degradation 3.Fault coverage 4.Ease of Implementation 5.Capability for system test 6.Diagnosis capability Built-In Self-Test (BIST) Issues
Page 5EL/CCUT T.-C. Huang May 2004 TCH CCUT Typical BIST Techniques 1.Stored Vector Based (Pattern Generated) 1.Microinstruction support 2.Stored in ROM 2.Algorithmic Hardware Test Pattern Generators 1.Counter 2.Linear Feedback Shift Register 3.Cellular Automata 4.FSM (ASM) Based Design with BIST TestGood (or Not)
Page 6EL/CCUT T.-C. Huang May 2004 TCH CCUT Classification 1.Forms 1.Off-Line Functional Structural 2.On-Line Concurrent Parallel Pipeline Asynchronous Non-concurrent 2.Level 1.Production Testing 2.Field Testing 3.TPG for BIST 1.Exhaustive Testing 2.Pseudo-random Testing Weighted Adaptive 3.Pseudo-exhaustive Testing Counter-Based: Syndrome, Constant-Weight LFSR-Based: Shift/Scan, XOR, Condensed, Cyclic
Page 7EL/CCUT T.-C. Huang May 2004 TCH CCUT General BIST Architecture CUT ORATPG ORATPG CUT ORATPG ORATPG ORA TPG DIST BISTC CUT ORA TPG DIST BISTC Embedded Separate CentralizedDistributed TPG: Test Pattern Generator, ORA: Output Result Analyzer CUT: Circuit under Test, BISTC: BIST Controller
Page 8EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture ArchitectureRef.Remark CSBL Benowitz, 1975Centralized & Separate Board-Level BIST BEST Resnick, 1983Built-In Evaluation and Self-Test RTS Bardell, 1982Random Test Socket LOCST Eichelberger, 1983LSSD On-Chip Self-Test STUMPS Bardell, 1982Self-Testing Using MISR and Parallel SRSG CBIST Saluja, 1988Concurrent BIST CEBS Komanytsky, 1982Centralized and Embedded BIST with Boundary Scan RTD Bardell, 1987Random Test Data SST Gupta, 1982Simultaneous Self-Test CATS Burkness, 1987Cyclic Analysis Testing System CSTP Krasniewski, 1989Circular Self-Test Path BILBO Koenemann, 1979Built-In Logic-Block Observation
Page 9EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture ArchitectureRef.ControlCircuitOn-lineBoundaryScan CSBL Benowitz, 1975CentralizedSeparateV BEST Resnick, 1983CentralizedSeparate V RTS Bardell, 1982DistributedSeparate VLSSD LOCST Eichelberger, 1983CentralizedSeparate VLSSD STUMPS Bardell, 1982CentralizedSeparate VMultiple CBIST Saluja, 1988CentralizedSeparateV CEBS Komanytsky, 1982CentralizedEmbedded V RTD Bardell, 1987DistributedEmbedded SST Gupta, 1982DistributedEmbedded No LFSR CATS Burkness, 1987CentralizedSeparate CSTP Krasniewski, 1989CentralizedSeparate BILBO Koenemann, 1979DistributedEmbedded
Page 10EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (1) CSBL CUT (C or S) MUX SISRCounter PRPG n k 1 m n m 1 PIs POs 1.Centralized and Separate Board-Level BIST [Benowitz 75] 2.Use only one Signature Register 3.Tests repeat m times to reduce hardware cost
Page 11EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (2) CombinationalSequential LFSR Combinational circuit SA LFSR Combinational circuit SA (Circular BIST)(BEST) 1.Pseudo random testing 2.Hardware overhead is low 3.Test length can be long for CUT with random-pattern resistant faults.
Page 12EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (3) RTS CUT (S) S in S out ClocksControls PRPG MISR SRPG R1R1 R3R3 R2R2 SISR R4R4 BIST controller 1.Combine LSSD Scan Chain and BIST 2.Can insert scan points to reduce test length for random- pattern resistant faults
Page 13EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (4) LOCST 1.Boundary scan is required to unify the test architecture 2.Single scan chain may cause high test time overhead. CUT (S) SiSi S0S0 SRSG PIs SRL R1R1 SISR POs SRL R2R2 On-chip monitor (OCM) Error-detection circuitry S in Error signal Control signals
Page 14EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (5) CBIST 1.Detect test patterns from normal inputs sequence 2.Once a pattern is detected, compress the response and tick the test clock. 3.If waited too long, insert a test pattern from PRPG. Comparator PRPG MUX N / T Normal inputs CUT (C) MISR Normal outputs EN CBIST Circuitry
Page 15EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (6) Circuit Under Test Shift registerLFSR SA LFSR SA SRSR SRSR SRSR CUT (CEBS)(STUMPS) Self-Testing using MISR & Parallel SRSGCentralized and Embedded BIST with BS low cost version of RTS or LOCST
Page 16EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (7) LFSR 1/83/41/27/81/2 LFSR Based Weighted Pseudo Random Test
Page 17EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (8) SST CUT Combinational PO PI 1.Similar to MISR but without LFSR part
Page 18EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (9) HP Focus Chip (Stored Pattern) 1.Chip Summaries 1.450,000 NMOS devices, 300,000 Nodes 2.24MHz Clocks, 300K bits of on-chip ROM 3. Used in HP computer 2.BIST Micro-program 1.Use microinstructions dedicated for testing 2.100K-bit BIST micro program in CPU ROM 3.Executes 20 million clock cycles 4.Greater than 95% stuck-at coverage 5.A power-up test used in system test, filed test, and wafer test
Page 19EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (10A) Motivation of BILBO Combinational Circuit Di Si Dn Ci Normal MISR RPG Scan
Page 20EL/CCUT T.-C. Huang May 2004 TCH CCUT Specific BIST Architecture (10B) Built-in Logic Block Observation (Koenemann ‘79) C1C1 BILBO1 BILBO2 C2C2 BILBO3 C3C3 B 1 B 2 BILBO 0 0shift register 0 1reset 1 0MISR (input constant LFSR) 1 1parallel load (normal operation)
Page 21EL/CCUT T.-C. Huang May 2004 TCH CCUT IDDQ Testing Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability
Page 22EL/CCUT T.-C. Huang May 2004 TCH CCUT VLSI Testing Theoretical Classification By Signals Modes: Voltage Test Current Test By Signal Types: Digital (Logic) Testing Analogue Testing
Page 23EL/CCUT T.-C. Huang May 2004 TCH CCUT IDDQ Testing Basic Concept V DD Current Sensor I DD t t
Page 24EL/CCUT T.-C. Huang May 2004 TCH CCUT IDDQ Testing Advantages 1.Can detect more physical defects including bridging defects. 2.The error response is easily detected by deep submicron era. 3.The ATPG is easily to design. 4.The test size (pattern count) is usually small. 5.Current test technology is sufficient.
Page 25EL/CCUT T.-C. Huang May 2004 TCH CCUT Types of IDDQ Test Architecture ATE Automatic Test Equipment DUT Device under Test External Motoring Test Fixture Off-Chip Current Monitor DUT Device under Test Test Fixture ATE Automatic Test Equipment BICS Built-In Current Sensor DUT Device under Test Built-In Current Test QTAG (Quality Test Action Group),1993
Page 26EL/CCUT T.-C. Huang May 2004 TCH CCUT Power Dissipation Static Power Dissipation V DD Dynamic Power Dissipation Switching Transient (Short-circuit) Current Loading Dissipation (Charging/Discharging of C L ) V DD
Page 27EL/CCUT T.-C. Huang May 2004 TCH CCUT Power Dissipation Pd Psc Ps Sub-micron Micron Deep- submicron Nano-meter 1m1m 80nm m 50%
Page 28EL/CCUT T.-C. Huang May 2004 TCH CCUT Power Dissipation Static Dissipation Quiescent State Input steady for enough time Either P- or N- Network is off Theoretically, IDDQ→0 However, small static dissipation due to Reverse bias leakage I SB Gate leakage Considerable in deep submicron era