Continuum Simulation for Power Integrity Analysis Raj Nair Dec. 16, 2010

December 2010 AnaSIM 2 Presentation Overview Background Background Methodology fundamentals Methodology fundamentals Examples Examples Benefits: chip floorplan optimization Benefits: chip floorplan optimization Tool demo Tool demo Conclusion Conclusion

December 2010 AnaSIM 3 Power Integrity Challenges: CPU Power doubles every ~36 months Transistors double every ~18 months Operating modes create load shifts Which create supply voltage ‘droops’, on-die Managed in part by package devices Mother Board Capacitors Microprocessor Heat Spreader Package Substrate Pentium™ is a trademark of Intel® Corporation

December 2010 AnaSIM 4 Decoupling Cap Loop-L Scaling and gives Load shift induced voltage noise equation and derivation of decap component characteristics scaling Inversely related to process scaling (on-die cap) & (freq. scaling) 2 65nm <<0.1pH! References: Nair 2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ 2002 Intel Technology Journal paper “Emerging Directions for Packaging…”Emerging Directions for Packaging

December 2010 AnaSIM 5 On-die L & L*di/dt challenge References: Nair 2008, Nair & Bennett 2008, Nair & Bennett 2010 EDADesignline “A Power Integrity Wall follows the Power Wall” & “Dynamic Voltage Droops & Total PI”, Prentice-Hall “PI Analysis & Mngmnt”A Power Integrity Wall follows the Power WallDynamic Voltage Droops & Total PIPI Analysis & Mngmnt PI degradation scales exponentially as k -1.5, where k is the process scaling factor (0.7 for example), regardless of constant-power scaling.

December 2010 AnaSIM 6 Motivation Atomic or Abstract? Atomic or Abstract? Analyze ripples by molecular interactions? Polygonal Analyses Polygonal Analyses Nanoscale IC’s face exploding, exponential computation complexity Energy & Efficiency Energy & Efficiency Must know IC’s ripples for lowest V supply

December 2010 AnaSIM 7 Meeting the Challenge Differential Power Differential Power Voltage is a potential difference; treat power grid differentially Partition hierarchically & exploit symmetry ECD: Continuum models ECD: Continuum models Grid is uniform; treat as a voltage-continuum along a single surface USPTO PUBUSPTO PUB Include R, L, C and solve ‘true-electromagnetically’ Abstract silicon, package Abstract silicon, package Include distributed models for silicon loads, CAP, pkg and board components

December 2010 AnaSIM 8 Abstraction & Physics-based Sims High levels of Abstraction High levels of Abstraction Power GRID as SURFACE Power GRID as SURFACE DISTRIBUTED circuit load currents & capacitance DISTRIBUTED circuit load currents & capacitance SYMMETRY in physical as well as electrical aspects SYMMETRY in physical as well as electrical aspects Comprehensive Modeling Comprehensive Modeling All grid electromagnetic properties, R, L, C used All grid electromagnetic properties, R, L, C used Actual block load current profiles used; di/dt, load activity factors included Actual block load current profiles used; di/dt, load activity factors included Physics based Simulation Physics based Simulation Field solver employed for Maxwell’s equations on ‘surfaces’ / NO ‘models’ Field solver employed for Maxwell’s equations on ‘surfaces’ / NO ‘models’

December 2010 AnaSIM 9 SoC Power Integrity Simulation Do CAPACITORS really absorb noise energy? 9 x 7mm chip 5nF /sq. cm distributed CAP 100mA peak noise pulse of 100ps width Power grid simulation Explicit CAP LENS Pulse noise source Differential noise R+L+C Dynamic Noise Simulation in  -fp Source: D. Bennett, ANASIM Corp.,  -fp power integrity aware floor planner, Animation slide Use slide show

December 2010 AnaSIM 10 Advanced SiP Simulation Near load systems Near load systems Active Noise Regulator* Active Noise Regulator* Distributed Local (POL) Voltage Regulators Distributed Local (POL) Voltage Regulators Spatial & Temporal Spatial & Temporal Power supply variation in x, y and t Power supply variation in x, y and t Data can feed into future Dynamic Timing Analysis? Data can feed into future Dynamic Timing Analysis? Simulation speed allows ‘what-if’ experiments for optimization Simulation speed allows ‘what-if’ experiments for optimization Chip power grid noise ANR attached to top left corner of grid Reference: * Nair & Bennett, ComLSIComLSI Power Management Designline article Animation slide Use slide show

December 2010 AnaSIM 11 Example: System-level Chip Sim GUI or Netlist capture GUI or Netlist capture Chip NETLIST Chip NETLISTNETLIST Load current profiles are pulse100gap100 and pulse200gap200 Load current profiles are pulse100gap100 and pulse200gap200 pulse100gap100 pulse200gap200 pulse100gap100 pulse200gap200 SYMMETRY in physical as well as electrical aspects SYMMETRY in physical as well as electrical aspects Experiment-1 results Experiment-1 results Chip grid ANIMATION & Mirror Chip grid ANIMATION & MirrorANIMATION MirrorANIMATION Mirror Notice substantial voltage variation of top left corner Notice substantial voltage variation of top left corner Cap 200pF added: results Cap 200pF added: results Chip grid ANIMATION & Mirror Chip grid ANIMATION & MirrorANIMATION MirrorANIMATION Mirror  -fp simulation schematic illustration (hyperlinked image)

December 2010 AnaSIM 12 Floorplanning / Optimization GRID wire width, spacing, pitch GRID wire width, spacing, pitch Metal resource savings, routing / timing facilitation Metal resource savings, routing / timing facilitation DECAP optimization DECAP optimization Area savings Area savings Block placement tweaks for PI Block placement tweaks for PI Noise generation, propagation Noise generation, propagation Chip-Package-Board early co-simulation Chip-Package-Board early co-simulation Operating voltage (Energy) tuning Operating voltage (Energy) tuning Resonance detection and avoidance… Resonance detection and avoidance…

December 2010 AnaSIM 13 Summary Continuum modeling facilitates high levels of abstraction and physics-based analyses for power integrity Continuum modeling facilitates high levels of abstraction and physics-based analyses for power integrity True-electromagnetic simulations feasible True-electromagnetic simulations feasible Simulation speed permits “what-if” expts. Simulation speed permits “what-if” expts. Chip resource optimization prior to place and route / physical design Chip resource optimization prior to place and route / physical design Facilitates low power/energy design Facilitates low power/energy design