ECE 448: Lab 6 DSP and FPGA Embedded Resources (Digital Downconverter)

Lab 6 Top Level Input Buffer Output Buffer EPP Interface TunerFilter WAV Format PC

Task 1 : PC Communication (20%) Input arrives asynchronously Input FIFO provides synchronous data to DDC. Output FIFO allows asynchronous access to the output data. Output Buffer is 4096 bytes. Inputs larger than ~16000 bytes will need to be sent and read in segments.

Task 1 : FIFO and EPP Interface Connections EPP (Code Provided) In FIFO EppAstbEppDstbEppWrEppDBEppWait 8 8 busOut din wr_en Out FIFO … dout rd_en din busIn dout rd_en

EPP UCF Assignments

Task 1: File Transfer Demo

Task 2: Tuner / NCO (15%) Switches form 5-bit Frequency Control Word, corresponding to a frequency f chosen from (0,0.5,1.0,…15.5) kHz. f = 0.5*sw(4:0) in kHz 20-bit accumulator: sum[n] = sum[n-1] + inc Update accumulator every valid_in pulse (on for one clock) Tuner sw[4:0] step data data_in valid valid_in Valid_out data_out 5 8 8

bit signed cosine values in a Lookup Table (LUT) Cosine values stored in 1 inferred or instantiated Block RAM 10 MSBs of accumulator used to address the LUT Output data_out = data_in * cos(accum(19:10)) every valid_in pulse Task 2: Cosine Lookup and Modulation

Task 2: Simulating Analog Signals Change the signal property in the simulation application to: Show the waveform in analog form Change the height of the analog waveform Change the radix of the signal to signed or unsigned

Task 3: Decimating FIR Filter (30%) 32 tap FIR Filter using serial approach 1 Multiplier, can be inferred or instantiated 32 8-bit samples stored in 16 instantiated SRLC16E primitives Starts processing when valid input is high (high for one clock cycle) Generates a valid output pulse (on for one clock) Output downsampled by a factor of 4 FIR Filter data data_in valid valid_in valid_out data_out 8 8

Finite Impulse Response (FIR) Filters FIR: Given an impulse input, the filter output goes to zero in a finite number of clocks because there is no feedback of the output to the input Filter: manipulate the frequency response Examples: low-pass, high-pass, band pass, notch, arbitrary Equation: y: output x: input h: filter coefficients a.k.a filter taps N: number of coefficients

Low Pass Filter

Serial Approach Output every N clocks One multiplier Two input Adder Multiply-Accumulate (MACC) Note the bit growth

Parallel Approach Output every clock One multiplier per tap N-input adder x[n]: shift register h[n]: stored constants Note the bit growth

Parallel-Serial Approach K multipliers Output every N/2 clocks 2+1 input Adder Multiply-Accumulate (MAC) Note the bit growth

Task 3: Downsampling Low-pass anti-aliasing filter Sample output of filter once every R samples. Direct implementation not an efficient way of downsampling (Task 6) Down-sampling by 3: fir_out

Task 3: Saturation Example 17 bit input Saturate 1 bit, round to 8 bits

Task 3: SRLC16E Primitive See pages for full instantiation template

Task 3: Data Buffer See pages for full instantiation template … x0x0 x1x1 x7x7 Sample k-31 … Addr[3:0] … Addr[4] dout Sample k Sample k-2

Task 4: Full DDC Operation (20%) Data can be played back in MATLAB, or by any media player after completion of Task 7. Output should be clear, with minimal background static and no high pitched noises.

Task 5: Parallel-Serial Operation (15%) Modify Task 3 to use two multipliers using parallel-serial approach Output values should remain the same Increase in resource utilization Decrease in latency

Tasks 6 and 7: Optimized Downsampling Task 6: Bonus(10%), Task 7: Bonus (10%) Only interested in every fourth sample. Calculate only y[4i]. Don’t bother calculating y[4i+1], y[4i+2], y[4i+3].

Task 8: WAV Format Bonus (10%) WAV Header added to beginning of output data stream. Data Format : PCM Sample Rate kHz Assume known data stream length (5510 bytes). Length fields may be larger Data stored in little-endian order

CORE Generator Demonstration