Estimation of IQ vector components of RF field - Theory and implementation M. Grecki, T. Jeżyński, A. Brandt

Agenda Introduction - LLRF system Downconversion and IQ estimation VHDL implementation of IQ estimator Sources of incorrectness Simulation and optimization of IQ estimation parameters (IF, SF) Conclusion

Agenda Introduction - LLRF system Downconversion and IQ estimation VHDL implementation of IQ estimator Sources of incorrectness Simulation and optimization of IQ estimation parameters (IF, SF) Conclusion

FPGA FTPZT Klystron ADC DAC Digital feedback ~ ~~ wave guide tuner HV cav.1 RF power waveguide ADC rf switch ~ Ainc Aref timing DOOCS server VME beam IQ wector modulator Control panel FTPZT ADC DAC ~ wave guide tuner cav.n ADC ~ Ainc Aref.... LO - Local Oscillator FPGA computational algorithm [a ij ]  + Feed forward table Gain table Setpoint table [b ij ] [z ij ]... cav A cav B cav Z + LLRF control system

Agenda Introduction - LLRF system Downconversion and IQ estimation VHDL implementation of IQ estimator Sources of incorrectness Simulation and optimization of IQ estimation parameters (IF, SF) Conclusion

Problem: signal downconversion I and Q estimation x if =x rf ·x lo x rf x lo x if  lo  F(  )   rf  rf -  lo  rf +  lo

Sampling of downconverted signal

System migration Future: IF = 81MHz ? SF = 36MHz ? TS = 1us many samples per TS averaging possible (noise reduction) Now: IF = 250kHz SF = 1MHz TS = 1us 4 samples / IF signal period prediction needed

AD Conversion parameters Constant SF (time uniform sampling) M·IF=N·SF (M,N –integer numbers) TS=1  s, IF >= 1MHz SF >= 3MHz, limited by ADC parameters SF - averaging => noise reduction SF - ADC accuracy drops down IF - ADC accuracy drops down

Agenda Introduction - LLRF system Downconversion and IQ estimation VHDL implementation of IQ estimator Sources of incorrectness Simulation and optimization of IQ estimation parameters (IF, SF) Conclusion

IQ estimation IF=81MHz, SF=36MHz entity IQestim is port (I : buffer BREG; -- I output Q : buffer BREG; -- Q output iqr : out bit; -- IQ output ready S : in BREG; -- sample input sr : in bit; -- sample ready input clk : in bit; reset : in bit); end; I reset clk sr iqr Q S

Numerical algorithm sincos xixi  18x18  14b int 24b int >>8 >>5 32b int *int(2 18 /M) >>17 IQ 14b int >>5 *int(2 18 /M) >>17 28b int < x i < < sin, cos < The computation algorithm assures ~14bits accuracy of results

VHDL implementation Design Summary Target Device : x2v4000 Target Package : ff1152 Target Speed : -6 Logic Utilization: Total Number Slice Registers: 64 out of 46,080 1% Number used as Flip Flops: 62 Number used as Latches: 2 Number of 4 input LUTs: 55 out of 46,080 1% Logic Distribution: Number of occupied Slices: 43 out of 23,040 1% Number of Slices containing only related logic: 43 out of % Number of Slices containing unrelated logic: 0 out of 43 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 80 out of 46,080 1% Number used as logic: 55 Number used as a route-thru: 25 Number of bonded IOBs: 46 out of 824 5% IOB Flip Flops: 29 Number of MULT18X18s: 4 out of 120 3% Number of GCLKs: 2 out of 16 12% Design statistics: Minimum period: ns (Maximum frequency: MHz)

Agenda Introduction - LLRF system Downconversion and IQ estimation VHDL implementation of IQ estimator Sources of incorrectness Simulation and optimization of IQ estimation parameters (IF, SF) Conclusion

Accuracy of ADC - AD6645 (1)

Accuracy of ADC - AD6645 (2)

Frank Ludwig /

Agenda Introduction - LLRF system Downconversion and IQ estimation VHDL implementation of IQ estimator Sources of incorrectness Simulation and optimization of IQ estimation parameters (IF, SF) Conclusion

Results of simulations error error rmserror max

IF=81MHz SF=36MHz Vn=0.5mV jit=5ps IF=81MHz SF=72MHz Vn=0.5mV jit=5ps Aerr(mean,std,min,max)= / / / PHI(mean,std,min,max)= / / / deg. Aerr(mean,std,min,max)= / / / PHI(mean,std,min,max)= / / / deg.

IF=81MHz, Vn=0.5mV, jit=5ps IF=9MHz, Vn=0.5mV, jit=5ps Error vs SF

SF=36MHz, Vn=0.5mV, jit=5ps SF=72MHz, Vn=0.5mV, jit=5ps Error vs IF

S shapeU shape Nonlinearity of ADC Nonlinearity does hardly influence phase

Agenda Introduction - LLRF system Downconversion and IQ estimation VHDL implementation of IQ estimator Source of incorrectness Simulation and optimization of IQ estimation parameters (IF, SF) Conclusion

Algorithm of IQ calculation is straightforward Its implementation in FPGA is simple and uses few resources The results of IQ calculation by Matlab script and VHDL model is identical the IF frequency should be chosen low (e.g. 9MHz) the SF frequency should be chosen high, limited by ADC SNR raise (e.g. 72MHz) all the noise sources and jitters should be identified and their influence on IQ estimation error investigated

Thank you for your attention. Questions?

Some maths.... when we sample x(t) we can say that we measure real part of complex RF vector in rotating coordinate system RF  x from this equations I and Q have to be calculated I Q

Some more maths.... LS where that is constant for given conversion scheme that needs calculation

Some math tricks... that is true if M  =k*360deg